Latest Digital ICs Industry White Papers

Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture,…

Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.

This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new…

This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.

Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.

Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.

This pocket guide evaluates these aspects as well as important considerations in making accurate power rail measurements…

This pocket guide evaluates these aspects as well as important considerations in making accurate power rail measurements and how impedance measurements can help to detect typical root causes of power integrity issues.

This eBook covers an approach that allows for the design of a myriad of interface standards without increasing design…

This eBook covers an approach that allows for the design of a myriad of interface standards without increasing design and verification time.

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on…

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on cloud hardware resources to satisfy peak demand usage can increase productivity and expedite turnaround times.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization…

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization that can drastically reduce the number of simulations required. It also discusses how the tools achieve the aforementioned while still ensuring designs will perform reliably in conformance with their design specifications over the lifetime of the products in which they are used. 

This white paper looks at the challenges of ever-increasingly complex designs packed into each die and explores…

This white paper looks at the challenges of ever-increasingly complex designs packed into each die and explores techniques that can be used to close designs efficiently and deliver them on time.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to…

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown.…

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown. Additionally, explore how companies can establish guidelines to ensure that usage is as efficient and cost-effective as possible.

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how…

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how safety mechanism effectiveness is evaluated.

This white paper discusses how NXP was able to reduce power without severely compromising features and performance…

This white paper discusses how NXP was able to reduce power without severely compromising features and performance dramatically. It also provides a closer look at how the i.MX 7ULP applications processor brings the benefits of a rich OS to battery-powered devices.

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be…

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.

Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce…

Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce time-to-market and innovate faster, simply by taking advantage of flexible resources and economies of scale.