Latest Digital ICs Industry White Papers

Design complexities and time-to-market pressures compel companies to find innovative ways to leverage all available…

Design complexities and time-to-market pressures compel companies to find innovative ways to leverage all available resources. Understanding the cost/ benefit relationship of cloud computing helps companies determine the optimal configuration that provides the greatest returns.

As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS Recon tool…

As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market.

Modern society is underpinned by electronics and electrical machines – it’s hard to imagine life without the myriad…

Modern society is underpinned by electronics and electrical machines – it’s hard to imagine life without the myriad of devices that keep us productive, comfortable, informed and entertained, both at home and in business. The development of new semiconductor technologies provide the right mix of features for current and emerging power conversion applications.

In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software…

In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software development.

This white paper explores the journey of understanding how to meet quality requirements and accelerate time-to-market for…

This white paper explores the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing (HPC) artificial intelligence (AI)-enabled system-on-chip (SoC) design.

Accelerate IC release-to-market and enhance customer experience with this white paper

Accelerate IC release-to-market and enhance customer experience with this white paper

Learn from this panel of experts addressing artificial intelligence's impact on the on the semiconductor industry,…

Learn from this panel of experts addressing artificial intelligence's impact on the on the semiconductor industry, specifically, chip design verification.

Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture,…

Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.

This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new…

This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.

Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.

Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.

This pocket guide evaluates these aspects as well as important considerations in making accurate power rail measurements…

This pocket guide evaluates these aspects as well as important considerations in making accurate power rail measurements and how impedance measurements can help to detect typical root causes of power integrity issues.

This eBook covers an approach that allows for the design of a myriad of interface standards without increasing design…

This eBook covers an approach that allows for the design of a myriad of interface standards without increasing design and verification time.

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on…

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on cloud hardware resources to satisfy peak demand usage can increase productivity and expedite turnaround times.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization…

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization that can drastically reduce the number of simulations required. It also discusses how the tools achieve the aforementioned while still ensuring designs will perform reliably in conformance with their design specifications over the lifetime of the products in which they are used. 

This white paper looks at the challenges of ever-increasingly complex designs packed into each die and explores…

This white paper looks at the challenges of ever-increasingly complex designs packed into each die and explores techniques that can be used to close designs efficiently and deliver them on time.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.