This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT…
This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.
This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.
This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.
This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown.…
This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown. Additionally, explore how companies can establish guidelines to ensure that usage is as efficient and cost-effective as possible.
This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how…
This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how safety mechanism effectiveness is evaluated.
This white paper discusses how NXP was able to reduce power without severely compromising features and performance…
This white paper discusses how NXP was able to reduce power without severely compromising features and performance dramatically. It also provides a closer look at how the i.MX 7ULP applications processor brings the benefits of a rich OS to battery-powered devices.
This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be…
This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.
Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce…
Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce time-to-market and innovate faster, simply by taking advantage of flexible resources and economies of scale.
Developing cost-effective industrial image processing systems requires high-performance cameras and flexible…
Developing cost-effective industrial image processing systems requires high-performance cameras and flexible image-processing systems capable of adaption.
Source control systems have become ubiquitous in the IT world but have not become a major component of operational…
Source control systems have become ubiquitous in the IT world but have not become a major component of operational technology (in particular, PLC programming). There is an increasing, popular movement in the industrial controls world to bring modern source control systems to PLC programming.
High speed PHYs, such as industry’s recent DDR5/LPDDR5 operating at 6400 Mbps and high-speed SerDes, heavily rely on…
High speed PHYs, such as industry’s recent DDR5/LPDDR5 operating at 6400 Mbps and high-speed SerDes, heavily rely on on-die clock distribution networks for clock and data transmission.
The advent of cloud computing nearly 20 years ago has led to a steady migration of computational resources…
The advent of cloud computing nearly 20 years ago has led to a steady migration of computational resources from corporate data centers to the cloud.
One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference…
One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year.
Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for…
Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for evaluating circuit reliability, particularly for noise and voltage drop analysis and ESD protection verification.
Design companies and foundries are constantly modifying their design implementation flow to deliver the best possible…
Design companies and foundries are constantly modifying their design implementation flow to deliver the best possible solution for their operational needs and the best possible designs for the market.
Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a…
Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor.
The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC…
The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC signal chain, including DAC intrinsic errors that vary depending on the system, can significantly disrupt the customer design-in experience.
The integration of multiple digital signal processing (DSP) blocks, wideband digital-to-analog converters (DACs), and…
The integration of multiple digital signal processing (DSP) blocks, wideband digital-to-analog converters (DACs), and wideband analog-to-digital converters (ADCs) within a single monolithic chip are enabling the offloading of FPGA resources.
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