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Category: All IP Cores (1032)

Open8 - 8-bit RISC Processor Core Based on the Automation uRISC

Open8 - 8-bit RISC Processor Core Based on the Automation uRISC

8-bit RISC processor core based on the Vautomation uRISC This is a "clean" reimplementation of the Vautomation uRISC processor core (aka…

License : BSD
Language : VHDL
oks8 - 8-bit External Data Bus Width for SAM87RI Instruction Set Execution

oks8 - 8-bit External Data Bus Width for SAM87RI Instruction Set Execution

The oks8 project is intended to provide a microcontroller in Verilog that like the KS86C4204/C4208/P4208 microcontroller (Samsung Inc.). It is…

License : GPL
Language : Verilog
OoOPs - Out-of-Order MIPS (TM) Processor

OoOPs - Out-of-Order MIPS (TM) Processor

OoOPs is intended to be a higher-performance alternative to other MIPS(TM)-compatible projects on OpenCores. Many of the other CPU cores are…

License : LGPL
Language : Verilog
ZAP - Pipelined ARM Compatible core with cache and MMU

ZAP - Pipelined ARM Compatible core with cache and MMU

ZAP : ARM compatible core with cache and MMU (ARMv4T ISA compatible) Author : Revanth Kamaraj (revanth91kamaraj@gmail.com) License : GPL v2…

License : GPL
Wishbone Version : B.3
Language : Verilog
OpenCores54x 16/32, Dual 16-bit DSP Core

OpenCores54x 16/32, Dual 16-bit DSP Core

The OpenCores54x (OC54x) DSP core is a cleanroom implementation of a popular family of DSPs designed by the No.1 DSP supplier from the southern…

OpenCPU32 Processor Module

OpenCPU32 Processor Module

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : VHDL
OpenFire Processor Core - Open-source, Binary-compatible MicroBlaze Clone

OpenFire Processor Core - Open-source, Binary-compatible MicroBlaze Clone

The OpenFire Processor Core is an open-source, binary-compatible MicroBlaze clone written in Verilog. Binary-compatible means exactly that - a…

Language : Verilog
OpenRISC 2000 Processor Architecture

OpenRISC 2000 Processor Architecture

Status of the OpenRISC 2000 WARNING! The development of the OpenRISC moved to OpenRISC.io The files contained in this repository are most likely…

License : LGPL
Language : Verilog
OpenRISC 1000 Processor Architecture

OpenRISC 1000 Processor Architecture

Status of the OpenRISC 1000 WARNING! The development of the OpenRISC moved to OpenRISC.io The files contained in this repository are most likely…

License : LGPL
Language : Verilog
OpenRisc 1200 HP, Hyper Pipelined OR1200 Core

OpenRisc 1200 HP, Hyper Pipelined OR1200 Core

The project is based on OpenCores' OR1200 project. The core is now hyper pipelined. It is a technique to multiply the functionality of a design…

License : LGPL
Language : Verilog
pAVR - 8-bit Controller With 6 Pipeline Stages

pAVR - 8-bit Controller With 6 Pipeline Stages

This project implements an 8 bit controller that is compatible with Atmel's AVR architecture, using VHDL (Very High speed integrated circuits…

PDP-11/70 CPU Core and SoC with Complete DEC PDP-11 System

PDP-11/70 CPU Core and SoC with Complete DEC PDP-11 System

Fig D-1: A PDP-11/70 Console. These display and switch consoles were the hallmark of the PDP-11 computers in the 70ties. Picture courtesy of Henk…

License : GPL
Language : VHDL
P16C5x - Emulation of PIC16C5x Single Cycle Core Implementation

P16C5x - Emulation of PIC16C5x Single Cycle Core Implementation

This project implements a single cycle core for the emulation of PIC16C5x microcomputers. The core requires the integrator to implement the I/O…

License : LGPL
Language : Verilog
Plasma with FPU - Based on MIPS I implementation

Plasma with FPU - Based on MIPS I implementation

This project is based on an implementation of MIPS I specified core by Steve Rhoads: plasma Interface entity plasma is generic( core_idx : natural…

License : Others
Language : VHDL
Configurable PDP-8 Processor Core and System

Configurable PDP-8 Processor Core and System

The PDP-8 was one of the earliest minicomputers and was in use from the mid 1960s into the 1980s. Because the PDP-8 was relatively inexpensive and…

License : GPL
Language : VHDL
QUARK RISK - 8-bit RISC Microprocessor with Wishbone Interconnect for SoC

QUARK RISK - 8-bit RISC Microprocessor with Wishbone Interconnect for SoC

8bit RISC microprocessor designed with features like wishbone interconnect to provide it as a tool for System-on-Chip or core (ASIC, CISC…

License : LGPL
Language : Verilog & VHDL
Pepelatz MISC - 16-bit Processor Written on Verilog

Pepelatz MISC - 16-bit Processor Written on Verilog

About Pepelatz MISC is a very small 16-bite processor written on Verilog. It can be used for learning Verilog HDL and computer low-level architecture.

License : LGPL
Language : Verilog
Plasma CPU - Small Synthesizable 32-bit RISC Microprocessor

Plasma CPU - Small Synthesizable 32-bit RISC Microprocessor

The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART,…

License : Others
Language : VHDL
S1 Core - 64-bit SPARC v9 Core with Wishbone Master Interface

S1 Core - 64-bit SPARC v9 Core with Wishbone Master Interface

S1 Core briefly... The S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor…

License : GPL
Language : Verilog
Potato Processor - Simple RISC-V Processor for use in FPGA Designs

Potato Processor - Simple RISC-V Processor for use in FPGA Designs

Development of the Potato Processor has moved to GitHub, check it out on https://github.com/skordal/potato Notable features are: Supports the full…

License : BSD
Language : VHDL