Latest EDA Tools Industry White Papers

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on…

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on cloud hardware resources to satisfy peak demand usage can increase productivity and expedite turnaround times.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.

This white paper displays how the Tanner flow simplifies the design and verification process of Analog/Mixed-Signal…

This white paper displays how the Tanner flow simplifies the design and verification process of Analog/Mixed-Signal design. It also describes how the user can verify design functionality, connectivity, and performance at all levels of the design hierarchy and for all integrated circuit (IC) applications.

This white paper walks through the design and review of a wiring harness for a small tractor using VeSys. Solutions like…

This white paper walks through the design and review of a wiring harness for a small tractor using VeSys. Solutions like the one discussed in this resource allow vehicle manufacturers to meet the demands of product complexity and quality while going to market faster than ever.

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization…

In this white paper, the reader will learn how the Calibre tools provide enhanced verification and fill optimization that can drastically reduce the number of simulations required. It also discusses how the tools achieve the aforementioned while still ensuring designs will perform reliably in conformance with their design specifications over the lifetime of the products in which they are used. 

This white paper looks at the challenges of ever-increasingly complex designs packed into each die and explores…

This white paper looks at the challenges of ever-increasingly complex designs packed into each die and explores techniques that can be used to close designs efficiently and deliver them on time.

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

This white paper demonstrates how using a production 7nm design, AMD achieved a 2.5X speed up in physical verification cycle time.

This white paper takes a look at how to replace inefficient, less precise verification processes with smarter, more…

This white paper takes a look at how to replace inefficient, less precise verification processes with smarter, more accurate, faster, and more efficient functionality that can improve both the bottom line and product quality.

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown.…

This white paper evaluates the necessity and value of EDA in the cloud while providing a cost-benefit breakdown. Additionally, explore how companies can establish guidelines to ensure that usage is as efficient and cost-effective as possible.

This white paper takes a closer look at how cloud processing provides companies the opportunity to reduce time to market…

This white paper takes a closer look at how cloud processing provides companies the opportunity to reduce time to market and speed up innovation while maintaining or lowering operating costs. This resource also describes what makes Core Calibre technology cloud-ready and its improvements in cloud security that eliminate industry concern over IP protection.

This paper provides an overview of the key characteristics of ON Semiconductor Gen 1 1200 V SiC MOSFETs and how they can…

This paper provides an overview of the key characteristics of ON Semiconductor Gen 1 1200 V SiC MOSFETs and how they can be influenced by the driving conditions. This resource also provides a guideline on the usage of the NCP51705 an isolated gate driver for SiC MOSFETs.

DDRx memory interfaces are key enablers for the technology that shapes modern life. Servers, computers, smartphones,…

DDRx memory interfaces are key enablers for the technology that shapes modern life. Servers, computers, smartphones, gaming consoles, and GPS systems are just some of the products that demand high-speed, high-bandwidth, double-data-rate memory. Each generation of DDRx DRAM brings new advantages that allow for faster, higher-capacity, and lower-power-consumption products.

Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce…

Moving some or all of your electronic design automation (EDA) computing to the cloud enables your company to reduce time-to-market and innovate faster, simply by taking advantage of flexible resources and economies of scale.

The advent of cloud computing nearly 20 years ago has led to a steady migration of computational resources…

The advent of cloud computing nearly 20 years ago has led to a steady migration of computational resources from corporate data centers to the cloud.

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference…

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year.

Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a…

Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor.

Early chip-level physical verification faces many challenges. The Calibre™ Recon tool enables design teams to perform…

Early chip-level physical verification faces many challenges. The Calibre™ Recon tool enables design teams to perform analysis and physical verification of full-chip design layouts during the very early stages of the design cycle, while the different components are still immature.