Download this white paper to learn how to simplify product development and increase security with modern platforms.
Download this white paper to learn how to simplify product development and increase security with modern platforms.
Need to improve harsh imaging conditions for security and surveillance cameras? Download this white paper to learn how…
Need to improve harsh imaging conditions for security and surveillance cameras? Download this white paper to learn how high dynamic range and intelligent linearization can help.
NEW tech paper - automated scalable power integrity analysis tool for analog designs
NEW tech paper - automated scalable power integrity analysis tool for analog designs
In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software…
In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software development.
MaaS is driving the need to add and improve features that support the heart of this new technology. This white paper…
MaaS is driving the need to add and improve features that support the heart of this new technology. This white paper explores how electronics and sensors are powering today's connected vehicles.
This white paper explores the journey of understanding how to meet quality requirements and accelerate time-to-market for…
This white paper explores the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing (HPC) artificial intelligence (AI)-enabled system-on-chip (SoC) design.
Learn the fundamentals of beamforming theory for phased array systems and its implementation in Xilinx Zynq®…
Learn the fundamentals of beamforming theory for phased array systems and its implementation in Xilinx Zynq® UltraScale+™ RFSoC.
Learn how to increase innovation and drive growth by modernizing digital product delivery.
Learn how to increase innovation and drive growth by modernizing digital product delivery.
Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture,…
Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.
This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new…
This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.
Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.
Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.
Explore how the Veloce® Strato emulation platform chip, operating system software, and hardware work together to enhance…
Explore how the Veloce® Strato emulation platform chip, operating system software, and hardware work together to enhance verification productivity.
This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce…
This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce the overall cost of ownership of their hardware verification resources even as it helps to accelerate the verification cycle.
Explore this unified software-enabled verification and validation environment that breaks the dependencies between…
Explore this unified software-enabled verification and validation environment that breaks the dependencies between hardware design groups and software developers.
Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.
Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.
Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…
Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.
This white paper addresses the most frequently asked questions developers have when choosing how to control and manage a…
This white paper addresses the most frequently asked questions developers have when choosing how to control and manage a multicore system.
This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also…
This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also demonstrates that the key to designers meeting this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.
Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…
Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.
This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to…
This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.
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