Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.
Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.
Explore how VirtuaLAB PCIe and Ethernet Virtual Machines (VM) work together, how they compete for host resources and how…
Explore how VirtuaLAB PCIe and Ethernet Virtual Machines (VM) work together, how they compete for host resources and how VMs address the big device management channel requirements for HW and SW co-verification in Veloce emulation.
This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new…
This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.
Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.
Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.
This white paper discusses the changes in storage technology and why SSD design teams need a complementary tool kit using…
This white paper discusses the changes in storage technology and why SSD design teams need a complementary tool kit using ICE, the Veloce Deterministic ICE App, and VirtuaLAB.
Explore how the Veloce® Strato emulation platform chip, operating system software, and hardware work together to enhance…
Explore how the Veloce® Strato emulation platform chip, operating system software, and hardware work together to enhance verification productivity.
This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce…
This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce the overall cost of ownership of their hardware verification resources even as it helps to accelerate the verification cycle.
Explore this unified software-enabled verification and validation environment that breaks the dependencies between…
Explore this unified software-enabled verification and validation environment that breaks the dependencies between hardware design groups and software developers.
Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.
Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.
Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…
Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.
Deciding to use a hypervisor or a multicore framework, or both, to control and manage a multicore system is a critical…
Deciding to use a hypervisor or a multicore framework, or both, to control and manage a multicore system is a critical architecture decision. This white paper provides information to help designers make the final decision that is dependent on the specific application requirements and the use case for their device.
This white paper covers the following medical safety, and device security, how to address security issues when they…
This white paper covers the following medical safety, and device security, how to address security issues when they arise, medical device certification, mixed-safety critical systems, the hardware platform, and the optimum use of hardware.
This white paper addresses the most frequently asked questions developers have when choosing how to control and manage a…
This white paper addresses the most frequently asked questions developers have when choosing how to control and manage a multicore system.
This paper outlines the key architectural considerations required for the successful operation of smart devices within an…
This paper outlines the key architectural considerations required for the successful operation of smart devices within an IIoT infrastructure with a focus on the software that runs on the device.
The global condition-based monitoring (CbM) market has experienced significant growth over the past few years, and it…
The global condition-based monitoring (CbM) market has experienced significant growth over the past few years, and it will likely only continue to grow in the near future. This growth coincides with the rapid advancement of MEMS accelerometers for use in vibration sensing applications, now rivaling the once-dominant piezoelectric (or PZT) accelerometer.
This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also…
This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also demonstrates that the key to designers meeting this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.
Discover deep insights into regulatory compliance tests, why it is important, its test challenges, and the solutions to…
Discover deep insights into regulatory compliance tests, why it is important, its test challenges, and the solutions to overcome these obstacles.
This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.
This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.
Building blocks of modern embedded systems, including processors, SoCs, system DRAM, non-volatile memories, sensors, and…
Building blocks of modern embedded systems, including processors, SoCs, system DRAM, non-volatile memories, sensors, and connectivity modules, have varied power requirements. On one extreme, a system power management IC (PMIC) integrates all or almost all of the required power rails. On the other hand, individual power rails are implemented using discrete dc/dc and LDOs.
Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…
Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.
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