Latest Embedded Industry White Papers

The global condition-based monitoring (CbM) market has experienced significant growth over the past few years, and it…

The global condition-based monitoring (CbM) market has experienced significant growth over the past few years, and it will likely only continue to grow in the near future. This growth coincides with the rapid advancement of MEMS accelerometers for use in vibration sensing applications, now rivaling the once-dominant piezoelectric (or PZT) accelerometer. 

This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also…

This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also demonstrates that the key to designers meeting this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.

Discover deep insights into regulatory compliance tests, why it is important, its test challenges, and the solutions to…

Discover deep insights into regulatory compliance tests, why it is important, its test challenges, and the solutions to overcome these obstacles.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.

This paper shows how manufacturing requirements can be leveraged to perform automated insertion of DRC/LVS-clean vias.

Building blocks of modern embedded systems, including processors, SoCs, system DRAM, non-volatile memories, sensors, and…

Building blocks of modern embedded systems, including processors, SoCs, system DRAM, non-volatile memories, sensors, and connectivity modules, have varied power requirements. On one extreme, a system power management IC (PMIC) integrates all or almost all of the required power rails. On the other hand, individual power rails are implemented using discrete dc/dc and LDOs.

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern…

Among the challenges for design-for-test (DFT) engineers is how to set a target metric for automatic test pattern generation (ATPG) and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected don’t consider the likelihood of one fault occurring compared to another.

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to…

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can for the first time implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how…

This white paper discusses faults and detectability by a safety mechanism, safety mechanism types and attributes, and how safety mechanism effectiveness is evaluated.

Explore how data analyses are being accelerated for autonomous vehicles.

Explore how data analyses are being accelerated for autonomous vehicles.

Learn how the long-established COM Express standard for Computer-on-Modules (COM) has been combined with a new…

Learn how the long-established COM Express standard for Computer-on-Modules (COM) has been combined with a new high-performance computing standard.

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be…

This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP solution can be used with multiple types of hosts by supporting legacy PCIe 4.0, USB4, USB 3.x, and USB 2.0 connections.

Source control systems have become ubiquitous in the IT world but have not become a major component of operational…

Source control systems have become ubiquitous in the IT world but have not become a major component of operational technology (in particular, PLC programming). There is an increasing, popular movement in the industrial controls world to bring modern source control systems to PLC programming.

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference…

One thing is clear — tapeouts are getting harder and taking longer. According to statistics from industry conference surveys, at least 50% of scheduled tapeouts slip each year.

Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for…

Accurately extracting and calculating the common resistance of interconnects within analog IC designs is fundamental for evaluating circuit reliability, particularly for noise and voltage drop analysis and ESD protection verification.

Design companies and foundries are constantly modifying their design implementation flow to deliver the best possible…

Design companies and foundries are constantly modifying their design implementation flow to deliver the best possible solution for their operational needs and the best possible designs for the market.

Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a…

Layout versus schematic (LVS) verification is an essential and integral part of integrated circuit (IC) verification in a system-on-chip (SoC) design cycle, but with today’s highly dense and hierarchical layouts, increasing circuit complexity, and intricate foundry rules, running LVS can be a time-consuming and resource-intensive endeavor.

Early chip-level physical verification faces many challenges. The Calibre™ Recon tool enables design teams to perform…

Early chip-level physical verification faces many challenges. The Calibre™ Recon tool enables design teams to perform analysis and physical verification of full-chip design layouts during the very early stages of the design cycle, while the different components are still immature.

The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC…

The monitoring and testing of a DAC signal chain are critical considerations for open-loop applications. Errors in a DAC signal chain, including DAC intrinsic errors that vary depending on the system, can significantly disrupt the customer design-in experience.

5G capabilities cover many different applications, standards, and capabilities. Enhanced mobile broadband (eMBB),…

5G capabilities cover many different applications, standards, and capabilities. Enhanced mobile broadband (eMBB), massive machine type communications (mMTC), and ultra-reliable low latency communications (URLLC) all contribute to the extended coverage and never-before-seen reliability with unparalleled accessibility.