Latest EDA Tools Industry White Papers

Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is…

Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is especially true when each substrate is built using a different methodology, team, and/or format.

Ensure correct-by-construction filler cell insertion in less time, while using standard industry interfaces that…

Ensure correct-by-construction filler cell insertion in less time, while using standard industry interfaces that seamlessly integrate with both the P&R and physical verification tools.

In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software…

In this white paper, the Siemens EDA tool provides a modular, scalable desktop prototyping platform for early software development.

This white paper explores the journey of understanding how to meet quality requirements and accelerate time-to-market for…

This white paper explores the journey of understanding how to meet quality requirements and accelerate time-to-market for your company’s latest flagship high performance computing (HPC) artificial intelligence (AI)-enabled system-on-chip (SoC) design.

In this case study, learn how the Aprisa software was able to implement a powerful and flexible RTL-GDSII design flow…

In this case study, learn how the Aprisa software was able to implement a powerful and flexible RTL-GDSII design flow that was easy to use, fast, technology ready, and with excellent correlation with sign-off to reduce iterations.

This white paper discusses how verification and validation bring the design of future cars to the present day.

This white paper discusses how verification and validation bring the design of future cars to the present day.

Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture,…

Learn how to create a new verification flow that combines emulation and X STEP, a platform that can generate, capture, and analyze bit-accurate fronthaul traffic.

Explore how VirtuaLAB PCIe and Ethernet Virtual Machines (VM) work together, how they compete for host resources and how…

Explore how VirtuaLAB PCIe and Ethernet Virtual Machines (VM) work together, how they compete for host resources and how VMs address the big device management channel requirements for HW and SW co-verification in Veloce emulation.

This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new…

This paper describes how a PreScan, Veloce, and AMEsim tool flow provides the thoroughness of verification to get new cars on the road quickly, efficiently, and safely.

Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.

Explore the advantages and benefits of Veloce VirtuaLAB emulation, backed up by three test cases.

This white paper discusses the changes in storage technology and why SSD design teams need a complementary tool kit using…

This white paper discusses the changes in storage technology and why SSD design teams need a complementary tool kit using ICE, the Veloce Deterministic ICE App, and VirtuaLAB.

Explore how the Veloce® Strato emulation platform chip, operating system software, and hardware work together to enhance…

Explore how the Veloce® Strato emulation platform chip, operating system software, and hardware work together to enhance verification productivity.

This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce…

This white paper discusses how SoC verification teams can achieve higher capacity than the desktop prototype and reduce the overall cost of ownership of their hardware verification resources even as it helps to accelerate the verification cycle.

Explore this unified software-enabled verification and validation environment that breaks the dependencies between…

Explore this unified software-enabled verification and validation environment that breaks the dependencies between hardware design groups and software developers.

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on…

This white paper from Siemens Digital Industries Software demonstrates how running Calibre PERC verification flows on cloud hardware resources to satisfy peak demand usage can increase productivity and expedite turnaround times.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Take a look at verification challenges and walk through a proven automated ESD verification methodology for 2.5D and 3D ICs.

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated…

Learn how to quickly and accurately analyze and fix (or waive) a wide range of complex error conditions with automated post-processing DRC debugging flows.

This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also…

This paper outlines the multi-dimensional nature of this complexity and the costs and opportunities it generates. It also demonstrates that the key to designers meeting this challenge is the ability to attain system-level visibility: both during the semiconductor development cycle, and subsequently after embedded systems are deployed in the field.

This white paper describes Siemens' new cloud-based solution and provides use-case examples. Readers will also get a…

This white paper describes Siemens' new cloud-based solution and provides use-case examples. Readers will also get a detailed description and testimonial from an early adopter.