Infineon says the new solution is an industry first for radiation-hardened NOR Flash.
Infineon says the new solution is an industry first for radiation-hardened NOR Flash.
In this deep dive, we take a look at how Winbond’s CUBE technology solves memory challenges for edge AI designs.
In this deep dive, we take a look at how Winbond’s CUBE technology solves memory challenges for edge AI designs.
AI will push the limits of PCs and smartphones. In turn, demands on storage controller chips will be intense. Learn how…
AI will push the limits of PCs and smartphones. In turn, demands on storage controller chips will be intense. Learn how chip architectures and firmware schemes must be optimized for these AI workloads.
New memory technologies, including HBM4, DDR5 DRAM, and MRAM, each respond to various industries outgrowing current…
New memory technologies, including HBM4, DDR5 DRAM, and MRAM, each respond to various industries outgrowing current storage infrastructure.
Investments in semiconductor manufacturing have been on the rise in recent years. Here are a few new examples.
Investments in semiconductor manufacturing have been on the rise in recent years. Here are a few new examples.
Startups are using and supporting AI in a myriad of ways.
Startups are using and supporting AI in a myriad of ways.
At this year's Future of Memory and Storage show, Microchip, Micron, and Samsung presented new memory solutions in the…
At this year's Future of Memory and Storage show, Microchip, Micron, and Samsung presented new memory solutions in the age of AI—from SSD controllers to LPDDR5X DRAM.
MCUs that only do control tasks are one thing. But in today’s AI age, a truly AI-enabled MCU needs to offer more. Learn…
MCUs that only do control tasks are one thing. But in today’s AI age, a truly AI-enabled MCU needs to offer more. Learn the important factors—from optimized neural processing units (NPUs) to power efficient architectures to clever memory topologies.
Teledyne e2v’s chips target space-based applications with significantly improved performance, protection against…
Teledyne e2v’s chips target space-based applications with significantly improved performance, protection against radiation, and spatial efficiency.
New transistors, memory devices, and RF modules defy the radiation-saturated conditions of space.
New transistors, memory devices, and RF modules defy the radiation-saturated conditions of space.
Weebit Nano and Efabless are teaming up to make it easier for chip designers to prototype intelligent devices using…
Weebit Nano and Efabless are teaming up to make it easier for chip designers to prototype intelligent devices using Weebit's advanced memory technology.
The new Pascari brand will provide SSDs for data-heavy enterprise applications.
The new Pascari brand will provide SSDs for data-heavy enterprise applications.
From embedded systems to high-performance storage, the latest memory advancements are stacking skyward to maximize…
From embedded systems to high-performance storage, the latest memory advancements are stacking skyward to maximize density and speed.
With speeds up to 143 MHz, the new 2-Mb and 4-Mb serial SRAM devices can be a lower-cost alternative to traditional…
With speeds up to 143 MHz, the new 2-Mb and 4-Mb serial SRAM devices can be a lower-cost alternative to traditional parallel SRAM products.
The CXL data protocol is essential for meeting the interconnect needs of today’s data centers. Learn the key elements…
The CXL data protocol is essential for meeting the interconnect needs of today’s data centers. Learn the key elements and benefits of this protocol, along with what’s new in CXL version 3.0.
Three companies—Samsung, Micron, and SK Hynix—have announced moves in the high-bandwidth memory (HBM) 3E market.
Three companies—Samsung, Micron, and SK Hynix—have announced moves in the high-bandwidth memory (HBM) 3E market.
In our final ISSCC spotlight, we explore Samsung's paper on a high-capacity, high-speed DDR5 memory that implements a…
In our final ISSCC spotlight, we explore Samsung's paper on a high-capacity, high-speed DDR5 memory that implements a monolithic-die-based 32-Gb DDR5 with 8 Gb/s/pin—all without leaving the 10 nm process.
The company’s UFS 4.0 solution meets AEC-Q100 Grade 2 requirements.
The company’s UFS 4.0 solution meets AEC-Q100 Grade 2 requirements.
Rambus' latest registering clock driver inches DDR5 memory closer to data center-level performance.
Rambus' latest registering clock driver inches DDR5 memory closer to data center-level performance.
Memory at both the HPC and edge levels may get a big leg up with help from magnetics.
Memory at both the HPC and edge levels may get a big leg up with help from magnetics.
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