Nissan has adopted Renesas's R-Car SOC and RH850 MCU for its ProPilot2 driver assistance system.
Nissan has adopted Renesas's R-Car SOC and RH850 MCU for its ProPilot2 driver assistance system.
What makes a secure SoC actually... secure? Check out this overview of hardware-based security features in a real-world…
What makes a secure SoC actually... secure? Check out this overview of hardware-based security features in a real-world example IC.
AI algorithms take a lot of resources to function. What hardware can handle running them on the edge?
AI algorithms take a lot of resources to function. What hardware can handle running them on the edge?
Using Microsemi PolarFire FPGAs, the new program aims to enable compact, high-bandwidth, low-power system design.
Using Microsemi PolarFire FPGAs, the new program aims to enable compact, high-bandwidth, low-power system design.
The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.
The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.
This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
As voice-activated digital assistant devices continue to gain popularity, AI- and audio-focused SoCs evolve.
As voice-activated digital assistant devices continue to gain popularity, AI- and audio-focused SoCs evolve.
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.
This article continues a discussion of microcontroller features and characteristics that are particularly important when…
This article continues a discussion of microcontroller features and characteristics that are particularly important when you’re thinking in terms of DSP capabilities.
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.
In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the…
In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the internal architecture.
Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction…
Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.
Huawei has chosen Dialog Semiconductor's DA14195 SoC for new wireless headphone devices.
Huawei has chosen Dialog Semiconductor's DA14195 SoC for new wireless headphone devices.
This article looks at the use cases and benefits of the arbiter with an implementation of a simple priority arbiter in VHDL.
This article looks at the use cases and benefits of the arbiter with an implementation of a simple priority arbiter in VHDL.
This week, Microsemi announced their latest unified design suite to help streamline the process of developing on FPGAs.
This week, Microsemi announced their latest unified design suite to help streamline the process of developing on FPGAs.
What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture?…
What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.
This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock…
This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock signal that will be used with an FPGA design.
This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and…
This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and function as a basic walkthrough of the Fast Fourier Transform interface.
This article will review the common FPGA resources that allow us to efficiently generate and distribute clock signals…
This article will review the common FPGA resources that allow us to efficiently generate and distribute clock signals throughout a system.
This article will look at the techniques that Vivado employs to accelerate design implementation.
This article will look at the techniques that Vivado employs to accelerate design implementation.
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