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Ep. 43 | Mark Papermaster: The EE and Exec Behind Apple, IBM, Cisco, and AMD’s Success

Ep. 43 | Mark Papermaster: The EE and Exec Behind Apple, IBM, Cisco, and AMD’s Success

What hasn’t Mark Papermaster accomplished? He’s the engineer and exec who impacted Apple’s iPhones and iPods, the IBM Power PC, and has led AMD's remarkable rejuvenation from a company that “may have lost their way” to surpassing Intel’s market cap.


The Pros and Cons of Moving EDA to the Cloud

The Pros and Cons of Moving EDA to the Cloud

Taking EDA to the cloud, Synopsys’ new software-as-a-service (SaaS) offerings for EDA and IC design raise the question: is cloud computing a good choice for chip design?


News Apr 11, 2022 by Jake Hertz
2D Semiconductors May Be Key to 3D Integration, Say Stanford Researchers

2D Semiconductors May Be Key to 3D Integration, Say Stanford Researchers

New research indicates how 2D semiconductors could advance monolithic 3D integration in a scalable way—prolonging Moore's law in the process.


News Apr 02, 2022 by vishvachi
Finding Your EE “Why” With Thy Tran: The “Semiconductor Gypsy”

Finding Your EE “Why” With Thy Tran: The “Semiconductor Gypsy”

In honor of Woman’s History Month, AAC talked with Micron’s Thy Tran who has made waves in the industry, inspiring new engineers and helping to bring groundbreaking DRAM technology to life.


News Mar 31, 2022 by Kimber Wymore
Ep. 42 | Groq CEO and Ex-Googler Jonathan Ross on the Petaflop AI Chip and First Ever TPU

Ep. 42 | Groq CEO and Ex-Googler Jonathan Ross on the Petaflop AI Chip and First Ever TPU

Groq’s chip architecture is something all electrical engineers will drool over. It not only focuses on high-performance computing (HPC), artificial intelligence (AI), and machine learning (ML), but it can do 1 PetaOp—1 quadrillion operations per second. “Which is four commas, not three... yeah,” Groq’s CEO Jonathan Ross emphasizes while confirming it is indeed 300X faster than NVIDIA’s chip. This “successful college dropout” designed Google’s TPU (tensor processing unit) and came up with $10B ideas at X - the moonshot factory, but “never in a million years” thought he’d be Groq’s CEO.


Chiplet Design Hopes to Rise Up as a Contender for Sidestepping Moore’s Law

Chiplet Design Hopes to Rise Up as a Contender for Sidestepping Moore’s Law

To overcome Moore's Law and die-to-die interconnection issues, the world’s top companies are turning to chiplet design for their next-generation computing hardware.


News Mar 28, 2022 by Jake Hertz
Photonic Wire Bonding Process Could Open Door to More Photonic Electronics

Photonic Wire Bonding Process Could Open Door to More Photonic Electronics

As photonics technology seeks its niche in the industry, one hurdle to overcome is a scalable fabrication process. One technique called photonic wire bonding (PWB) hopes to push photonics forward.


News Mar 26, 2022 by Abdulwaliy Oyekunle
Nvidia’s Hopper Architecture Leaps in With Tons of New Tech for HPC and AI

Nvidia’s Hopper Architecture Leaps in With Tons of New Tech for HPC and AI

Continuing to unpack NVIDIA's GTC Conference releases, one stand out was the Hopper architecture targeting high-performance computing (HPC) and AI/machine learning.


News Mar 24, 2022 by Jake Hertz
Designing to Protect 5G Macro Base Stations for High Reliability

Designing to Protect 5G Macro Base Stations for High Reliability

In this article, learn about protecting three major base station systems, the baseband unit, the power supply, and the backup battery system.


AAC Exclusive: A Chat With IBM Researchers Who Built the New “VTFET” Transistor

AAC Exclusive: A Chat With IBM Researchers Who Built the New “VTFET” Transistor

In December, IBM and Samsung announced a new transistor architecture said to defy conventional FinFETs. We spoke with two of IBM's leading researchers on this project for details.


News Mar 07, 2022 by Ingrid Fadelli
Indium Oxide Semiconductors May Keep Moore’s Law Going

Indium Oxide Semiconductors May Keep Moore’s Law Going

Researchers around the world are continually finding new ways to prolong Moore's law. Now, Purdue researchers have found another means to this end: using an atomic layer deposition technique for indium oxide-based transistors.


News Feb 28, 2022 by Darshil Patel
The “Traitorous Eight” and the Rise of Fairchild Semiconductor

The “Traitorous Eight” and the Rise of Fairchild Semiconductor

While Shockley Semiconductor may have been the first company of Silicon Valley, it was Fairchild Semiconductor—founded by eight former Shockley engineers—who proliferated thousands of tech companies.


News Feb 28, 2022 by Tyler Charboneau
GaN Keeps a Steady Pace Into 2022 With a Focus on Design

GaN Keeps a Steady Pace Into 2022 With a Focus on Design

The race to beat out silicon (Si) for the "best" semiconductor continues with a rush of gallium nitride (GaN) announcements focusing on creating and furthering GaN-based device designs.


SpaceX Loses 40 Satellites to Radiation: Spotlight on Rad-hard IC Design

SpaceX Loses 40 Satellites to Radiation: Spotlight on Rad-hard IC Design

Space, the "final frontier," has been a growing area of interest, especially for electronic devices. Companies like Microchip, BAE Systems, Intel, CAES, and Lattice Semiconductor take aim for better space-rated IC design.


News Feb 14, 2022 by Darshil Patel
EU Officially Puts Forward Its Own Chips Act

EU Officially Puts Forward Its Own Chips Act

The EU is following the U.S. in enacting its own chips act to stimulate the global semiconductor industry.


News Feb 10, 2022 by Jake Hertz
Revitalizing Charge Pump Techniques: NIST Improves Transistor Defect Detection

Revitalizing Charge Pump Techniques: NIST Improves Transistor Defect Detection

Researchers from the National Institute of Science and Technology (NIST) have brought an old charge pumping technique back to life to ensure transistor quality, revitalizing it as "Frequency Modulated Charge Pumping."


News Feb 07, 2022 by Jake Hertz
A Farewell to FinFETs: Intel Goes 3D With Stacked Forksheet Transistor

A Farewell to FinFETs: Intel Goes 3D With Stacked Forksheet Transistor

If pushing transistor scaling through advanced silicon field effect transistor (FET) structures like forksheet wasn’t enough, Intel is now looking to stack those transistors in the Z dimension for improved circuit density and performance.


News Jan 31, 2022 by Dale Wilson
Hazards in Combinational Logic Circuits

Hazards in Combinational Logic Circuits

This article covers undesired switching events, known as hazards, that can occur when developing combinational logic circuits.


Combinational Logic Circuit Design and Simulation Using Gates

Combinational Logic Circuit Design and Simulation Using Gates

Gate-level implementation of logic functions is limited by the gate fan-in. This article examines logic factoring, grouping, and level increases to implement logic functions with limited input gates.


Rekindled Focus on Space Exploration Yields Advances in Rad-hard ICs

Rekindled Focus on Space Exploration Yields Advances in Rad-hard ICs

As the goals for space exploration become more ambitious, the requirements of space-grade ICs are stacking high.


News Dec 24, 2021 by Ikimi .O