The leap from DDR4 and DDR5 is no incremental development. We're looking at a leap from standard frequencies of 2400 MHz to 4800 MHz.
May 16, 2020 by Antonio Anzaldua Jr.
There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.
May 12, 2020 by Kurt Shuler, Arteris
How does Micron's hefty memory hardware portfolio qualify them for this shift?
April 29, 2020 by Cabe Atwell
By nature, memory devices are built to last. But when it comes to industrial applications, these parts are expected to far outlast memory devices for consumer products.
April 28, 2020 by Amos Kingatua
Effectively storing data remains a key issue in modern information systems and a challenge for electronics engineers who need to design devices with the thought of robust data storage as a primary concern.
April 15, 2020 by Biljana Ognenova
In this article, we will look at a proposed non-volatile DRAM and how it compares to current memory technologies.
February 14, 2020 by Robin Mitchell
Micron says their LPDDR5 DRAM will allow 5G smartphones to have 6.4 Gbps peak processing while improving power efficiency by 20%.
February 07, 2020 by Gary Elinoff
The ISL70005SEH, geared for satellite orbit, incorporates both a synchronous buck converter and a low dropout (LDO) regulator in one monolithic IC.
January 31, 2020 by Gary Elinoff
The QN9090 and QN9030 are Bluetooth low-energy (BLE) devices that integrate Arm Cortex-M4 CPUs.
January 29, 2020 by Gary Elinoff
Micron claims that the new DDR5 will provide an 85% increase in memory performance in the next generation of server workloads.
January 07, 2020 by Lisa Boneta
The new series of SPI EERAM memory chips were designed to retain data during power loss without the aid of external batteries.
December 04, 2019 by Cabe Atwell
This article shows how to initialize arrays in a C program with values from text files.
September 25, 2019 by Stephen Colley
Learn how to use code memory to free up RAM on your MCU.
September 16, 2019 by Robert Keim
This article will explore what virtual memory is, why it exists, and how it works from a high level.
August 20, 2019 by Stephen St. Michael
This article will take a closer look at the commands used to control and interact with DRAM.
August 09, 2019 by Stephen St. Michael
This article will examine the basic operation of Dynamic Random Access Memory (DRAM), along with how a DRAM chip is organized.
August 01, 2019 by Stephen St. Michael
This article will examine principles of CPU cache design including locality, logical organization, and management heuristics.
July 11, 2019 by Stephen St. Michael
This week, Adesto Technologies introduced its new FusionHD non-volatile memories (NVMs).
March 03, 2019 by Gary Elinoff
In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold increase in performance with up to a 70% energy savings per bit compared to DDR3 DRAM.
January 22, 2019 by Ivan Kuten, Promwad
Here's a snapshot of some of the most recent developments in the implantable tech space.
December 26, 2018 by Gary Elinoff
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