There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache…
There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.
How does Micron's hefty memory hardware portfolio qualify them for this shift?
How does Micron's hefty memory hardware portfolio qualify them for this shift?
By nature, memory devices are built to last. But when it comes to industrial applications, these parts are expected to…
By nature, memory devices are built to last. But when it comes to industrial applications, these parts are expected to far outlast memory devices for consumer products.
Effectively storing data remains a key issue in modern information systems and a challenge for electronics engineers who…
Effectively storing data remains a key issue in modern information systems and a challenge for electronics engineers who need to design devices with the thought of robust data storage as a primary concern.
In this article, we will look at a proposed non-volatile DRAM and how it compares to current memory technologies.
In this article, we will look at a proposed non-volatile DRAM and how it compares to current memory technologies.
Micron says their LPDDR5 DRAM will allow 5G smartphones to have 6.4 Gbps peak processing while improving power efficiency by 20%.
Micron says their LPDDR5 DRAM will allow 5G smartphones to have 6.4 Gbps peak processing while improving power efficiency by 20%.
The ISL70005SEH, geared for satellite orbit, incorporates both a synchronous buck converter and a low dropout (LDO)…
The ISL70005SEH, geared for satellite orbit, incorporates both a synchronous buck converter and a low dropout (LDO) regulator in one monolithic IC.
The QN9090 and QN9030 are Bluetooth low-energy (BLE) devices that integrate Arm Cortex-M4 CPUs.
The QN9090 and QN9030 are Bluetooth low-energy (BLE) devices that integrate Arm Cortex-M4 CPUs.
Micron claims that the new DDR5 will provide an 85% increase in memory performance in the next generation of server workloads.
Micron claims that the new DDR5 will provide an 85% increase in memory performance in the next generation of server workloads.
The new series of SPI EERAM memory chips were designed to retain data during power loss without the aid of external batteries.
The new series of SPI EERAM memory chips were designed to retain data during power loss without the aid of external batteries.
This article shows how to initialize arrays in a C program with values from text files.
This article shows how to initialize arrays in a C program with values from text files.
Learn how to use code memory to free up RAM on your MCU.
Learn how to use code memory to free up RAM on your MCU.
This article will explore what virtual memory is, why it exists, and how it works from a high level.
This article will explore what virtual memory is, why it exists, and how it works from a high level.
This article will take a closer look at the commands used to control and interact with DRAM.
This article will take a closer look at the commands used to control and interact with DRAM.
This article will examine the basic operation of Dynamic Random Access Memory (DRAM), along with how a DRAM chip is organized.
This article will examine the basic operation of Dynamic Random Access Memory (DRAM), along with how a DRAM chip is organized.
This article will examine principles of CPU cache design including locality, logical organization, and management heuristics.
This article will examine principles of CPU cache design including locality, logical organization, and management heuristics.
This week, Adesto Technologies introduced its new FusionHD non-volatile memories (NVMs).
This week, Adesto Technologies introduced its new FusionHD non-volatile memories (NVMs).
In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold…
In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold increase in performance with up to a 70% energy savings per bit compared to DDR3 DRAM.
Here's a snapshot of some of the most recent developments in the implantable tech space.
Here's a snapshot of some of the most recent developments in the implantable tech space.
Here is the profile of a fab that provides composition screening and stack engineering services for new materials used in…
Here is the profile of a fab that provides composition screening and stack engineering services for new materials used in the next-generation memory devices.