Latest CPUs Articles and Videos

FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a…

FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a hard-instantiated RISC-V core.

Housed in a familiar form factor, Milk-V’s latest SBC tackles embedded compute problems with RISC-V processing.

Housed in a familiar form factor, Milk-V’s latest SBC tackles embedded compute problems with RISC-V processing.

Emerging from stealth mode, HaiLa believes they can enable a future of IoT nodes without batteries.

Emerging from stealth mode, HaiLa believes they can enable a future of IoT nodes without batteries.

Adil Kidwai, VP and Head of Product Management at EdgeQ, discusses how they are aiming to redefine software-defined…

Adil Kidwai, VP and Head of Product Management at EdgeQ, discusses how they are aiming to redefine software-defined radios as they build what they believe is the world’s first base station-on-a-chip, using RISC-V to enable AI and 5G.

New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.

New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.

Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize”…

Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize” artificial intelligence (AI).

SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.

SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.

With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.

With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.

The company has emerged from stealth mode with a new paradigm in the RISC-V industry.

The company has emerged from stealth mode with a new paradigm in the RISC-V industry.

The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.

The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.

The latest chip from Renesas adds voice recognition to the industry’s RISC-V ecosystem.

The latest chip from Renesas adds voice recognition to the industry’s RISC-V ecosystem.

With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s…

With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s RISC-V cores.

With the new processor, the company hopes to bring a feature-rich set of functions to the RISC-V community.

With the new processor, the company hopes to bring a feature-rich set of functions to the RISC-V community.

The crowd funded LapPi 2.0 laptop offering could give the DIY community a new way to learn about personal computers.

The crowd funded LapPi 2.0 laptop offering could give the DIY community a new way to learn about personal computers.

Catch up on some of the technology and industry trends we’ve noticed from 2022.

Catch up on some of the technology and industry trends we’ve noticed from 2022.

In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a…

In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer the flexibility needed to drive innovation.

At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.

At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.

At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and…

At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs.

Aiming to usurp Arm processors in size-constrained, compute hungry designs like wearables, SiFive has expanded its RISC-V…

Aiming to usurp Arm processors in size-constrained, compute hungry designs like wearables, SiFive has expanded its RISC-V “Performance” line of processors.