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Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit

Server-class RISC-V Core Unveiled by Ventana at RISC-V Summit

In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer the flexibility needed to drive innovation.


News Dec 19, 2022 by Aaron Carman
“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes

“RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes

At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.


News Dec 16, 2022 by Jeff Child
5 Online EE Resources I WOULD Have Been Thankful For

5 Online EE Resources I WOULD Have Been Thankful For

On this Thanksgiving Day, Jeff wonders what his EE college days would have been like if he’d had access to All About Circuits’ rich online resources.


News Nov 24, 2022 by Jeff Child
IBM Touts SoC as Solution for Faster Deep Learning Training

IBM Touts SoC as Solution for Faster Deep Learning Training

With its new SoC, IBM hopes to pave the way for AI training and performance that can one day be 1,000 times faster than modern solutions.


News Oct 20, 2022 by Jake Hertz
Your Back-to-School Guide to All About Circuits’ Educational Resources

Your Back-to-School Guide to All About Circuits’ Educational Resources

For students back in college for their Fall semester—and anyone who needs a refresher—here’s the lowdown on our top-notch textbooks, technical articles, and calculators for EE studies.


News Oct 12, 2022 by Jeff Child
Arm Sues Qualcomm Over NUVIA’s Custom Cores

Arm Sues Qualcomm Over NUVIA’s Custom Cores

Arm has accused Qualcomm of breaching its licenses and wants the chipmaker to destroy its NUVIA CPU designs, plus offering up compensation.


News Sep 05, 2022 by Chantelle Dubois
Siemens EDA Launches Revamped Mixed-signal IC Verification Platform

Siemens EDA Launches Revamped Mixed-signal IC Verification Platform

At this week’s Design Automation Conference (DAC), Siemens EDA rolled out a next generation version of its mixed-signal IC verification tool adding new capabilities.


News Jul 12, 2022 by Jeff Child
An Introduction to RISC-V—Understanding RISC’s Open ISA

An Introduction to RISC-V—Understanding RISC’s Open ISA

This article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical description of the modular ISA, and some commercial RISC-V microprocessor implementations.


The “Traitorous Eight” and the Rise of Fairchild Semiconductor

The “Traitorous Eight” and the Rise of Fairchild Semiconductor

While Shockley Semiconductor may have been the first company of Silicon Valley, it was Fairchild Semiconductor—founded by eight former Shockley engineers—who proliferated thousands of tech companies.


News Feb 28, 2022 by Tyler Charboneau
Chipmakers Petition for Language Change in Funding Bill to Include Mission-Critical Devices

Chipmakers Petition for Language Change in Funding Bill to Include Mission-Critical Devices

A bill currently going through Congress which would see semiconductor firms handed an extra $3 billion in funding could do more harm than good if its language isn’t modified, some defense firms have said.


News Nov 07, 2020 by Luke James
As Moore’s Law Ends, Samsung Releases 3D IC Technology

As Moore’s Law Ends, Samsung Releases 3D IC Technology

Samsung announced the availability of its 3D IC technology at both 7nm and 5nm. How does this technology help system designers?


News Aug 17, 2020 by Jake Hertz
Cadence to Acquire AWR for $160 Million to Simplify RF IC Design

Cadence to Acquire AWR for $160 Million to Simplify RF IC Design

Cadence and National Instruments are ramping up their collaborations to a strategic alliance to facilitate the design process of RF integrated circuits.


News Dec 09, 2019 by Gary Elinoff
AXI Interconnects Tutorial: Multiple AXI Masters and Slaves in Digital Logic

AXI Interconnects Tutorial: Multiple AXI Masters and Slaves in Digital Logic

This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.


Obtaining Convergence for High-Q XTAL Oscillators

Obtaining Convergence for High-Q XTAL Oscillators

Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso Periodic Steady State (PSS) analysis.


The Journey of RISC-V Implementation

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.


IC Design Resources Roundup: Mentor, Cadence, and Synopsys

IC Design Resources Roundup: Mentor, Cadence, and Synopsys

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.


Miller Frequency Compensation: How to Use Miller Capacitance for Op-Amp Compensation

Miller Frequency Compensation: How to Use Miller Capacitance for Op-Amp Compensation

Miller capacitance is commonly used in a method for operational amplifier frequency compensation.


Shunt Capacitance Compensation in Operational Amplifiers

Shunt Capacitance Compensation in Operational Amplifiers

In this article, we'll discuss how shunt capacitance can be used to achieve frequency compensation in op-amps and we'll also see why this is not the preferred technique.


An Introduction to SweRV, a RISC-V Core

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.


Learn Analog Circuits: Types and Applications of Current Mirrors

Learn Analog Circuits: Types and Applications of Current Mirrors

The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and current-mode signal processing.