In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer…
In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer the flexibility needed to drive innovation.
At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.
At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.
On this Thanksgiving Day, Jeff wonders what his EE college days would have been like if he’d had access to All About…
On this Thanksgiving Day, Jeff wonders what his EE college days would have been like if he’d had access to All About Circuits’ rich online resources.
With its new SoC, IBM hopes to pave the way for AI training and performance that can one day be 1,000 times faster than…
With its new SoC, IBM hopes to pave the way for AI training and performance that can one day be 1,000 times faster than modern solutions.
For students back in college for their Fall semester—and anyone who needs a refresher—here’s the lowdown on our…
For students back in college for their Fall semester—and anyone who needs a refresher—here’s the lowdown on our top-notch textbooks, technical articles, and calculators for EE studies.
Arm has accused Qualcomm of breaching its licenses and wants the chipmaker to destroy its NUVIA CPU designs, plus…
Arm has accused Qualcomm of breaching its licenses and wants the chipmaker to destroy its NUVIA CPU designs, plus offering up compensation.
At this week’s Design Automation Conference (DAC), Siemens EDA rolled out a next generation version of its mixed-signal…
At this week’s Design Automation Conference (DAC), Siemens EDA rolled out a next generation version of its mixed-signal IC verification tool adding new capabilities.
This article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical…
This article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical description of the modular ISA, and some commercial RISC-V microprocessor implementations.
While Shockley Semiconductor may have been the first company of Silicon Valley, it was Fairchild Semiconductor—founded…
While Shockley Semiconductor may have been the first company of Silicon Valley, it was Fairchild Semiconductor—founded by eight former Shockley engineers—who proliferated thousands of tech companies.
A bill currently going through Congress which would see semiconductor firms handed an extra $3 billion in funding could…
A bill currently going through Congress which would see semiconductor firms handed an extra $3 billion in funding could do more harm than good if its language isn’t modified, some defense firms have said.
Samsung announced the availability of its 3D IC technology at both 7nm and 5nm. How does this technology help system designers?
Samsung announced the availability of its 3D IC technology at both 7nm and 5nm. How does this technology help system designers?
Cadence and National Instruments are ramping up their collaborations to a strategic alliance to facilitate the design…
Cadence and National Instruments are ramping up their collaborations to a strategic alliance to facilitate the design process of RF integrated circuits.
This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.
This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso…
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso Periodic Steady State (PSS) analysis.
In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when…
In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.
The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.
The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.
Miller capacitance is commonly used in a method for operational amplifier frequency compensation.
Miller capacitance is commonly used in a method for operational amplifier frequency compensation.
In this article, we'll discuss how shunt capacitance can be used to achieve frequency compensation in op-amps and we'll…
In this article, we'll discuss how shunt capacitance can be used to achieve frequency compensation in op-amps and we'll also see why this is not the preferred technique.
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.
The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and…
The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and current-mode signal processing.