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Microsemi Releases Libero SoC 12.0, a New Unified Design Suite for SoC FPGA Development

Microsemi Releases Libero SoC 12.0, a New Unified Design Suite for SoC FPGA Development

This week, Microsemi announced their latest unified design suite to help streamline the process of developing on FPGAs.


News Jan 31, 2019 by Robin Mitchell
FPGA Design Software: An Overview of Time-to-Integration Features in Xilinx’s Vivado Design Suite

FPGA Design Software: An Overview of Time-to-Integration Features in Xilinx’s Vivado Design Suite

This article will look at some of the most important features of the Xilinx Vivado Design Suite which accelerates the "time to integration" of the design procedure.


News Aug 24, 2018 by Dr. Steve Arar
ASICs Wanted: The BM1387 and the Hardware Designed for Cryptocurrency Mining

ASICs Wanted: The BM1387 and the Hardware Designed for Cryptocurrency Mining

Cryptocurrencies have been in and out of the news for a while now. Because "mining" is the only source of new cryptocurrency units, complex ASIC devices such as the BM1387 have been created to aid in the mining process. Here's a look at some ASICs that aims to make mining faster and more effective.


News Aug 02, 2018 by Robin Mitchell
Making the Cloud More Powerful: Xilinx FPGAs and Adaptive Workload Acceleration

Making the Cloud More Powerful: Xilinx FPGAs and Adaptive Workload Acceleration

Historically, FPGAs have been challenging to work with. To combat that reputation, Xilinx developed programmable devices that simplify—and accelerate—the implementation of customized hardware development.


An Introductory Project for Software Defined Radio

An Introductory Project for Software Defined Radio

Learn how to listen to frequencies on the air with nothing more than a USB dongle: first FM radio, then voice signals.


Projects Feb 02, 2017 by Christi Durham
Embedded FPGA: Changing the Way Chips Are Designed

Embedded FPGA: Changing the Way Chips Are Designed

Learn how embedded FPGAs work and what advantages they offer.


Microsoft Proposes FPGA-Assisted Servers to Gain Speed at the End of Moore’s Law

Microsoft Proposes FPGA-Assisted Servers to Gain Speed at the End of Moore’s Law

Microsoft uses programmable chips to offer an accelerated implementation for a number of algorithms such as machine learning, pattern matching, and more.


News Nov 07, 2016 by Dr. Steve Arar
Implementing a Finite State Machine in VHDL

Implementing a Finite State Machine in VHDL

Impress your friends and family by learning how to implement a finite state machine in VHDL