The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.
The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.
This article describes the benefits and requirements of the internal RC oscillator often available inside many low-cost…
This article describes the benefits and requirements of the internal RC oscillator often available inside many low-cost Microcontroller units, including the calibration procedure to obtain the best possible accuracy.
Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.
Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.
Cadence and National Instruments are ramping up their collaborations to a strategic alliance to facilitate the design…
Cadence and National Instruments are ramping up their collaborations to a strategic alliance to facilitate the design process of RF integrated circuits.
Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that…
Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.
The new 7nm SoC is the first device in a chipset family offering integrated 5G modems.
The new 7nm SoC is the first device in a chipset family offering integrated 5G modems.
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of…
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.
This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.
This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.
In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the…
In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.
These recently-released FPGAs aim to use accessible programming languages, withstand harsh environments, and support ASIC…
These recently-released FPGAs aim to use accessible programming languages, withstand harsh environments, and support ASIC prototyping.
This article describes a methodology that automates set up, constraints, and results analysis as designs move from static…
This article describes a methodology that automates set up, constraints, and results analysis as designs move from static CDC analysis to formal verification to simulation and avoid manual scripting efforts, thus reducing setup effort and errors.
This article looks at factors that can alter the functionality of a bipolar junction transistor (BJT) by causing…
This article looks at factors that can alter the functionality of a bipolar junction transistor (BJT) by causing variations in its forward current gain.
Google’s OpenTitan is a collaborative venture with tech companies that offers multi-factor security keys and RoT…
Google’s OpenTitan is a collaborative venture with tech companies that offers multi-factor security keys and RoT technology, which will be baked into new chips.
Dialog Semiconductor today announced a new BLE SoC—one it claims is the smallest and least power-hungry on the market.
Dialog Semiconductor today announced a new BLE SoC—one it claims is the smallest and least power-hungry on the market.
The die-to-die PHY IP enables extra-short reach connectivity in multi-chip modules (MCM) for hyper-scale data centers,…
The die-to-die PHY IP enables extra-short reach connectivity in multi-chip modules (MCM) for hyper-scale data centers, AI, and networking applications.
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso…
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso Periodic Steady State (PSS) analysis.
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of…
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.
The MLX90821 measures pressures that dip down to 50 mbars in the EVAP systems of internal combustion or hybrid engines.
The MLX90821 measures pressures that dip down to 50 mbars in the EVAP systems of internal combustion or hybrid engines.
This article discusses the issues surrounding trace-width calculation and provides a solid foundation for designing your…
This article discusses the issues surrounding trace-width calculation and provides a solid foundation for designing your next high-current net.
Robust NVM (non-volatile memory) can now more easily co-exist with power functions on the same chip.
Robust NVM (non-volatile memory) can now more easily co-exist with power functions on the same chip.
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