Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
At the 2023 North America RISC-V Summit, dozens of presenters will showcase RISC-V innovations in desktop computing and…
At the 2023 North America RISC-V Summit, dozens of presenters will showcase RISC-V innovations in desktop computing and wearable applications.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects…
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects to large-scale corporate initiatives.
Hailed for his historic microprocessor designs at AMD, Apple, and Broadcom, Jim Keller is onto his next CPU endeavor at…
Hailed for his historic microprocessor designs at AMD, Apple, and Broadcom, Jim Keller is onto his next CPU endeavor at Tenstorrent.
Renesas, Infineon, Edge Impulse, and AnalogLamb have released boards and kits—all with the goal of accelerating…
Renesas, Infineon, Edge Impulse, and AnalogLamb have released boards and kits—all with the goal of accelerating development cycles in embedded systems.
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a…
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a hard-instantiated RISC-V core.
Housed in a familiar form factor, Milk-V’s latest SBC tackles embedded compute problems with RISC-V processing.
Housed in a familiar form factor, Milk-V’s latest SBC tackles embedded compute problems with RISC-V processing.
Emerging from stealth mode, HaiLa believes they can enable a future of IoT nodes without batteries.
Emerging from stealth mode, HaiLa believes they can enable a future of IoT nodes without batteries.
The new Root of Trust IP from Rambus offers post-quantum cryptography hardware solutions.
The new Root of Trust IP from Rambus offers post-quantum cryptography hardware solutions.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
Three of Agile Analog's IP subsystems for battery-powered IoT solutions are entering the RISC-V ecosystem.
Three of Agile Analog's IP subsystems for battery-powered IoT solutions are entering the RISC-V ecosystem.
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize”…
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize” artificial intelligence (AI).
SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.
SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.
While there are differences between edge AI, end-point AI, and TinyML, each of these fields is progressing real-time…
While there are differences between edge AI, end-point AI, and TinyML, each of these fields is progressing real-time processing in its own ways. Below is a roundup of recent news in these three areas.
With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.
With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.
The company has emerged from stealth mode with a new paradigm in the RISC-V industry.
The company has emerged from stealth mode with a new paradigm in the RISC-V industry.
The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.
The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.
The latest chip from Renesas adds voice recognition to the industry’s RISC-V ecosystem.
The latest chip from Renesas adds voice recognition to the industry’s RISC-V ecosystem.
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