At a NYC press and analyst dinner, MediaTek executives described how the company's custom XPU works with NVIDIA and plans to move beyond the smartphone market.
At a NYC press and analyst dinner, MediaTek executives described how the company's custom XPU works with NVIDIA and plans to move beyond the smartphone market.
Discover how enhanced neural processing and memory simplify system development to deliver low-latency, power-efficient…
Discover how enhanced neural processing and memory simplify system development to deliver low-latency, power-efficient intelligence at the edge without cloud reliance.
Asian Development Bank (ADB) is advancing Asia's semiconductor sector by expanding workforce training in Thailand and…
Asian Development Bank (ADB) is advancing Asia's semiconductor sector by expanding workforce training in Thailand and offering financial de-risking tools to strengthen supply chain resilience.
Seymour Cray assembled the 1976 Cray-1 from a dual 5/4 NAND gate, a bipolar register chip, and a 1,024-bit Isoplanar RAM,…
Seymour Cray assembled the 1976 Cray-1 from a dual 5/4 NAND gate, a bipolar register chip, and a 1,024-bit Isoplanar RAM, all in ECL and largely from Fairchild.
Renesas UX leader Ivo Marocco explores physical AI and intelligence at the edge. He details how autonomous systems and…
Renesas UX leader Ivo Marocco explores physical AI and intelligence at the edge. He details how autonomous systems and humanoid robots must be developed responsibly, safely, and efficiently.
Efinix expands its Sapphire RISC-V SoC family with a configurable 64-bit processor offering larger memory support, Linux…
Efinix expands its Sapphire RISC-V SoC family with a configurable 64-bit processor offering larger memory support, Linux capability and FPGA acceleration for embedded and edge AI designs.
Intel, AMD, and Arm each made agentic AI announcements this week at OCP 2026, covering rack processor units, rack…
Intel, AMD, and Arm each made agentic AI announcements this week at OCP 2026, covering rack processor units, rack architecture, and benchmarking
The X7 runs on 2-5 W, connects over PCIe Gen 3 or USB 3.2, and uses the same CVflow engine already in over 50 million of…
The X7 runs on 2-5 W, connects over PCIe Gen 3 or USB 3.2, and uses the same CVflow engine already in over 50 million of the company’s AI SoCs.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
After building a $10B+ smartphone business, Yenchi Lee is standing up MediaTek's Datacenter BU from scratch to tackle…
After building a $10B+ smartphone business, Yenchi Lee is standing up MediaTek's Datacenter BU from scratch to tackle full-stack AI silicon, 2.5D packaging, and co-packaged optics.
The RZ/G3L and RZ/G3SE share a pin-compatible package platform and 1-mW-level standby power.
The RZ/G3L and RZ/G3SE share a pin-compatible package platform and 1-mW-level standby power.
A new addition to Nvidia's CUDA-Q quantum computing platform adds logical qubit error correction and abstraction to…
A new addition to Nvidia's CUDA-Q quantum computing platform adds logical qubit error correction and abstraction to significantly speed reliable quantum application development.
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices…
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices highlight growing investment in AI infrastructure, quantum manufacturing, optical connectivity, and edge intelligence.
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring…
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring flagship AI performance to fanless Googlebooks.
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end…
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end compute and proactive mobile intelligence.
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development…
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference architecture to eliminate tail latency, maximize power efficiency, and scale agentic AI clusters.
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve…
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve 1.2 TB/s of unified memory bandwidth.
The Q-2390 and IQ-2390 share a Cortex-A78/A55 complex, an Adreno 704 GPU, and an optional RISC-V real-time core, with the…
The Q-2390 and IQ-2390 share a Cortex-A78/A55 complex, an Adreno 704 GPU, and an optional RISC-V real-time core, with the industrial part introducing the IQ2 Series.
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4…
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4 platform provide specialized architectures for agentic AI workloads across various domains.
The 2-nm processor runs Arm and z/Architecture instructions natively on the same core.
The 2-nm processor runs Arm and z/Architecture instructions natively on the same core.
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