The new registering clock driver raises registered DIMM data rates to 9,600 MT/s for CPU-based servers.
The new registering clock driver raises registered DIMM data rates to 9,600 MT/s for CPU-based servers.
In this edition of Business Shorts, SK Group and Nvidia plan $500 billion in AI infrastructure, TDK and LG Innotek team…
In this edition of Business Shorts, SK Group and Nvidia plan $500 billion in AI infrastructure, TDK and LG Innotek team up on robotic sensing, and Micron locks in automotive memory supply.
The new modular 1RU cybersecurity test platform, delivers 400 Gbps throughput for validating modern AI and hyperscale…
The new modular 1RU cybersecurity test platform, delivers 400 Gbps throughput for validating modern AI and hyperscale network infrastructure under heavy traffic demands.
The PM1763 pairs a newly developed 4-nm controller with ninth-generation V-NAND, more than doubling the throughput of…
The PM1763 pairs a newly developed 4-nm controller with ninth-generation V-NAND, more than doubling the throughput of Samsung's fastest PCIe 5.0 enterprise drive.
In this Q&A with Vicor, we explore current multiplication and decoupled conversion stages. Both overcome traditional…
In this Q&A with Vicor, we explore current multiplication and decoupled conversion stages. Both overcome traditional multiphase limitations and drastically cut I²R thermal losses for high-demand loads.
Launched today, Synopsys’ ESUN IP solution slashes AI tail latency and eliminates networking bottlenecks to enable…
Launched today, Synopsys’ ESUN IP solution slashes AI tail latency and eliminates networking bottlenecks to enable seamless, scalable performance for modern AI infrastructure.
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language…
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language models at lower cost per token.
The 120 MHz GD32E512 is optimized for high-speed optical modules and the 72 MHz GD32E252 takes on low-speed optical modules.
The 120 MHz GD32E512 is optimized for high-speed optical modules and the 72 MHz GD32E252 takes on low-speed optical modules.
Thread Group and Broadband Forum are partnering to unify IoT mesh with broadband infrastructure. Also, the new Thread…
Thread Group and Broadband Forum are partnering to unify IoT mesh with broadband infrastructure. Also, the new Thread Tools app launches to provide real-world network diagnostics for engineers.
The new XpressConnect PCIe 6.0 and CXL 3.1 Retimers reign in signal integrity challenges in AI data centers and other…
The new XpressConnect PCIe 6.0 and CXL 3.1 Retimers reign in signal integrity challenges in AI data centers and other high-bandwidth installations.
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network…
At Computex, Intel described the CPU as the control plane for agentic workloads, pairing new processors and network controllers with fresh details on its inference GPU.
The 88-core Vera processor introduces Spatial Multithreading and a claimed 1.8x task-completion lead over x86 processors.
The 88-core Vera processor introduces Spatial Multithreading and a claimed 1.8x task-completion lead over x86 processors.
The bottleneck limiting the next generation of artificial intelligence isn't compute power—it's the wire connecting the…
The bottleneck limiting the next generation of artificial intelligence isn't compute power—it's the wire connecting the chips. French startup Scintil Photonics thinks it has the answer.
Broadcom’s high-integration Wi-Fi 8 & NPU-accelerated 50G PON gateway SoCs aim to build a cohesive, 50 Gbps broadband…
Broadcom’s high-integration Wi-Fi 8 & NPU-accelerated 50G PON gateway SoCs aim to build a cohesive, 50 Gbps broadband access ecosystem for the AI-infused home.
A South Korean startup, KoolMicro, is betting that liquid cooling built into the chip package itself is the only way to…
A South Korean startup, KoolMicro, is betting that liquid cooling built into the chip package itself is the only way to handle the next generation of GPU heat loads.
The new switch IP targets AI and data center SoCs that need to move data efficiently across CPUs, GPUs, accelerators, and…
The new switch IP targets AI and data center SoCs that need to move data efficiently across CPUs, GPUs, accelerators, and NVMe storage without adding more physical lanes.
Cisco designed the Universal Quantum Switch to connect quantum systems using different encoding methods, marking a major…
Cisco designed the Universal Quantum Switch to connect quantum systems using different encoding methods, marking a major step toward scalable quantum networking over existing telecom infrastructure.
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs
The new plug-in module is designed to meet the timing and synchronization requirements of distributed computing, AI data…
The new plug-in module is designed to meet the timing and synchronization requirements of distributed computing, AI data centers, and upcoming 5G networks.
Learn how Korean AI technology company Rebellions uses proprietary dataflow NPUs, chiplets, and HBM to deliver…
Learn how Korean AI technology company Rebellions uses proprietary dataflow NPUs, chiplets, and HBM to deliver high-efficiency, scalable AI inference for modern data centers.
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