Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
Leveraging Synaptics’ partnership with Google Research, the new SoC is positioned between microcontroller-class devices…
Leveraging Synaptics’ partnership with Google Research, the new SoC is positioned between microcontroller-class devices and high-end embedded MPUs.
With its E1 processor announced today, Efficient Computer is hoping to usher in a new era of general-purpose computing efficiency.
With its E1 processor announced today, Efficient Computer is hoping to usher in a new era of general-purpose computing efficiency.
Enjoy this fresh crop of technology news from the Embedded World 2025 trade show in Nuremberg, Germany.
Enjoy this fresh crop of technology news from the Embedded World 2025 trade show in Nuremberg, Germany.
Enjoy this taste of the rich collection of technology news from the Embedded World North America trade show in Austin, Texas.
Enjoy this taste of the rich collection of technology news from the Embedded World North America trade show in Austin, Texas.
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe.
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe.
Check out the technologies and products these leading companies plan to showcase at next week's Embedded World trade show…
Check out the technologies and products these leading companies plan to showcase at next week's Embedded World trade show in Nuremberg, Germany.
While the rest of the world spent 2023 playing with ChatGPT, the electronics industry put AI into everything from…
While the rest of the world spent 2023 playing with ChatGPT, the electronics industry put AI into everything from processors to edge IoT chips to EDA tools.
Renesas has announced one of the first independently developed 32-bit RISC-V CPUs.
Renesas has announced one of the first independently developed 32-bit RISC-V CPUs.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
At the 2023 North America RISC-V Summit, dozens of presenters will showcase RISC-V innovations in desktop computing and…
At the 2023 North America RISC-V Summit, dozens of presenters will showcase RISC-V innovations in desktop computing and wearable applications.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects…
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects to large-scale corporate initiatives.
Hailed for his historic microprocessor designs at AMD, Apple, and Broadcom, Jim Keller is onto his next CPU endeavor at…
Hailed for his historic microprocessor designs at AMD, Apple, and Broadcom, Jim Keller is onto his next CPU endeavor at Tenstorrent.
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a…
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a hard-instantiated RISC-V core.
Housed in a familiar form factor, Milk-V’s latest SBC tackles embedded compute problems with RISC-V processing.
Housed in a familiar form factor, Milk-V’s latest SBC tackles embedded compute problems with RISC-V processing.
Emerging from stealth mode, HaiLa believes they can enable a future of IoT nodes without batteries.
Emerging from stealth mode, HaiLa believes they can enable a future of IoT nodes without batteries.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize”…
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize” artificial intelligence (AI).
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