Announced today, Altera has a new FPGA portfolio along with an AI expert companion designed to accelerate development for next-generation digital and physical AI fabrics.
Announced today, Altera has a new FPGA portfolio along with an AI expert companion designed to accelerate development for next-generation digital and physical AI fabrics.
Infineon Wi-Fi 7 technology enables smart home with seamless interoperability, advanced environmental sensing, and…
Infineon Wi-Fi 7 technology enables smart home with seamless interoperability, advanced environmental sensing, and energy-efficient connectivity.
Discover how enhanced neural processing and memory simplify system development to deliver low-latency, power-efficient…
Discover how enhanced neural processing and memory simplify system development to deliver low-latency, power-efficient intelligence at the edge without cloud reliance.
Asian Development Bank (ADB) is advancing Asia's semiconductor sector by expanding workforce training in Thailand and…
Asian Development Bank (ADB) is advancing Asia's semiconductor sector by expanding workforce training in Thailand and offering financial de-risking tools to strengthen supply chain resilience.
Seymour Cray assembled the 1976 Cray-1 from a dual 5/4 NAND gate, a bipolar register chip, and a 1,024-bit Isoplanar RAM,…
Seymour Cray assembled the 1976 Cray-1 from a dual 5/4 NAND gate, a bipolar register chip, and a 1,024-bit Isoplanar RAM, all in ECL and largely from Fairchild.
Renesas UX leader Ivo Marocco explores physical AI and intelligence at the edge. He details how autonomous systems and…
Renesas UX leader Ivo Marocco explores physical AI and intelligence at the edge. He details how autonomous systems and humanoid robots must be developed responsibly, safely, and efficiently.
Efinix expands its Sapphire RISC-V SoC family with a configurable 64-bit processor offering larger memory support, Linux…
Efinix expands its Sapphire RISC-V SoC family with a configurable 64-bit processor offering larger memory support, Linux capability and FPGA acceleration for embedded and edge AI designs.
Intel, AMD, and Arm each made agentic AI announcements this week at OCP 2026, covering rack processor units, rack…
Intel, AMD, and Arm each made agentic AI announcements this week at OCP 2026, covering rack processor units, rack architecture, and benchmarking
Timing failures rarely announce themselves. They usually surface as system instability. Join us for a look at how…
Timing failures rarely announce themselves. They usually surface as system instability. Join us for a look at how SiTime's precision timing solutions keep that dependency silent for decades.
The X7 runs on 2-5 W, connects over PCIe Gen 3 or USB 3.2, and uses the same CVflow engine already in over 50 million of…
The X7 runs on 2-5 W, connects over PCIe Gen 3 or USB 3.2, and uses the same CVflow engine already in over 50 million of the company’s AI SoCs.
Announced today at OCP Summit, Cisco and Nvidia have partnered on the open USFP optical spec, alongside new Cisco Silicon…
Announced today at OCP Summit, Cisco and Nvidia have partnered on the open USFP optical spec, alongside new Cisco Silicon One ASICs and runtime security to scale next-generation Ethernet AI fabrics.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
The OAX7700 ASIC adds an NPU and pre-roll video capture to cut parking surveillance power consumption by 97%.
The rapid deployment of AI workloads in data centers is driving new requirements for power electronics, including very…
The rapid deployment of AI workloads in data centers is driving new requirements for power electronics, including very high power density, fast load transients, and strict efficiency targets.
After building a $10B+ smartphone business, Yenchi Lee is standing up MediaTek's Datacenter BU from scratch to tackle…
After building a $10B+ smartphone business, Yenchi Lee is standing up MediaTek's Datacenter BU from scratch to tackle full-stack AI silicon, 2.5D packaging, and co-packaged optics.
In this interview article, Renesas VP Peter Jenkins discusses how the company is leveraging its automotive sensor…
In this interview article, Renesas VP Peter Jenkins discusses how the company is leveraging its automotive sensor heritage and mixed-signal ICs to power the future of edge AI and humanoid robotics.
The RZ/G3L and RZ/G3SE share a pin-compatible package platform and 1-mW-level standby power.
The RZ/G3L and RZ/G3SE share a pin-compatible package platform and 1-mW-level standby power.
A new addition to Nvidia's CUDA-Q quantum computing platform adds logical qubit error correction and abstraction to…
A new addition to Nvidia's CUDA-Q quantum computing platform adds logical qubit error correction and abstraction to significantly speed reliable quantum application development.
The SY757xx family translates clock inputs from 1.2 to 3.3 V down to 1.2 V LVCMOS outputs at frequencies up to 250 MHz,
The SY757xx family translates clock inputs from 1.2 to 3.3 V down to 1.2 V LVCMOS outputs at frequencies up to 250 MHz,
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices…
Recent semiconductor business moves from Nvidia, MediaTek, GlobalFoundries, Qualcomm, Amazon, and Analog Devices highlight growing investment in AI infrastructure, quantum manufacturing, optical connectivity, and edge intelligence.
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring…
Announced today, MediaTek's new 3 nm Dimensity CX C10 Max SoC features an all-big-core Arm CPU and NPU 890 to bring flagship AI performance to fanless Googlebooks.
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