Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
In this exclusive Embedded World 2025 interview, we talk to AMD’s Kirk Saban about edge AI, ASICs vs. FPGAs, Adaptive…
In this exclusive Embedded World 2025 interview, we talk to AMD’s Kirk Saban about edge AI, ASICs vs. FPGAs, Adaptive SoCs, embedded x86, and the outlook ahead.
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe.
At every point in the design process, RISC-V developers can make use of the advancements presented at RISC-V Summit Europe.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
Reporting a “banner year” for adoption, these RISC-V developments show the versatility of the ISA.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
The latest RISC-V IP makes processing power customizable for a wide span of embedded applications.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
SiFive has released two new processors, one to target machine learning applications, and one to target general-purpose HPC.
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects…
In this roundup, we review the ways RISC-V is making its mark in the computing world—from small-scale gaming projects to large-scale corporate initiatives.
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a…
FPGA vendor Gowin Semiconductor has teamed with RISC-V IP developer Andes Technology to develop an SRAM FPGA SoC with a hard-instantiated RISC-V core.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
New innovations from the RISC-V Summit Europe are poised to streamline the design process for open-source processors.
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize”…
Leveraging its proprietary in-memory compute scheme and RISC-V dataflow technology, Axelera AI seeks to “democratize” artificial intelligence (AI).
SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.
SiFive hopes to strengthen the RISC-V community with the contribution of its WorldGuard model.
With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.
With its 5G base-station-on-a-chip SoC leading the way, EdgeQ has closed a $75 million round of investment funding.
The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.
The new architecture has the secure element as the Master, while the CPU serves as the Subordinate.
With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s…
With their collaboration, the firms hope to enable faster and improved functional verification testing for Bluespec’s RISC-V cores.
With the new processor, the company hopes to bring a feature-rich set of functions to the RISC-V community.
With the new processor, the company hopes to bring a feature-rich set of functions to the RISC-V community.
Catch up on some of the technology and industry trends we’ve noticed from 2022.
Catch up on some of the technology and industry trends we’ve noticed from 2022.
In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a…
In a bid to bring RISC-V to the high-performance, data center computing space, Ventana announced their Veyron family, a series of processors positioned to offer the flexibility needed to drive innovation.
At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.
At the annual summit, leaders in the RISC-V community had much to say about RISC-V taking over the world.
At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and…
At this year’s RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs.
Aiming to usurp Arm processors in size-constrained, compute hungry designs like wearables, SiFive has expanded its RISC-V…
Aiming to usurp Arm processors in size-constrained, compute hungry designs like wearables, SiFive has expanded its RISC-V “Performance” line of processors.
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