By embedding heterogeneous Si, SiC, and GaN die directly into 12-inch silicon wafers with precision RDLs, Onsemi's EPP replaces wire bonds and mold compounds to…
By embedding heterogeneous Si, SiC, and GaN die directly into 12-inch silicon wafers with precision RDLs, Onsemi's EPP replaces wire bonds and mold compounds to deliver up to 5x power density.
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end…
The flagship system-on-chip pairs a 4th-generation All Big Core CPU and dual neural processing units to drive high-end compute and proactive mobile intelligence.
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development…
Launched today, Delos Data’s Nonstop AI portfolio intros Apollo Data Interface silicon, the Morpheus development platform, and a system-level reference architecture to eliminate tail latency, maximize power efficiency, and scale agentic AI clusters.
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve…
M6 is Apple's first 2-nm chip and features a dual 16-core Neural Engine, while the M5 Ultra joins four dies to achieve 1.2 TB/s of unified memory bandwidth.
The new evaluation kits aim to lower the barrier for on-device AI development with Alif’s AI/ML hardware-accelerated…
The new evaluation kits aim to lower the barrier for on-device AI development with Alif’s AI/ML hardware-accelerated Ensemble and Balletto MCUs.
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4…
Announced today, the company's new CSS for Mobile 2 platform, Total Design for Physical AI program, and Neoverse CSS N4 platform provide specialized architectures for agentic AI workloads across various domains.
Select Versal RF Series devices will be AMD's first adaptive SoCs with native UCIe 1.1 interfaces, allowing designers to…
Select Versal RF Series devices will be AMD's first adaptive SoCs with native UCIe 1.1 interfaces, allowing designers to co-package third-party chiplets.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
RackCommander groups MaxLinear's USB UARTs, RS-485 transceivers, GPIO expanders, and power devices for rack-level management.
Companies across industries are leveraging tech from NXP, MaxLinear and Nordic Semiconductor on automotive UWB,…
Companies across industries are leveraging tech from NXP, MaxLinear and Nordic Semiconductor on automotive UWB, accelerated OpenZFS storage, and low-power Bluetooth Mesh sensing.
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall…
In this edition of Business Shorts, we spotlight five announcements that show AI demand is reshaping everything from Wall Street financing to washing machines.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The new PolarFire FPGA-powered board from Microchip brings multiple sensors to Nvidia edge AI platforms.
The rebuilt platform puts the previously closed cloud backend under an Apache 2.0 license and runs on AWS serverless…
The rebuilt platform puts the previously closed cloud backend under an Apache 2.0 license and runs on AWS serverless services in a customer's own account.
The controller, PHY, security, and verification IP support 128 GT/s links and target rack-scale memory pools exceeding 100 TB.
The controller, PHY, security, and verification IP support 128 GT/s links and target rack-scale memory pools exceeding 100 TB.
The six new chips offer a wide range of connectivity and graphics options for wearables, hearables, AR devices, health…
The six new chips offer a wide range of connectivity and graphics options for wearables, hearables, AR devices, health monitors, industrial sensors, and beyond.
The new 2.2 A single-coil fan driver boasts code-free configuration, low-noise motor control, and integrated protection…
The new 2.2 A single-coil fan driver boasts code-free configuration, low-noise motor control, and integrated protection for GPU, data center, industrial, and appliance cooling applications.
Industry leaders used FMS 2026 to introduce a suite of new memory advancements, from denser QLC NAND to 16,000 MT/s DDR5.
Industry leaders used FMS 2026 to introduce a suite of new memory advancements, from denser QLC NAND to 16,000 MT/s DDR5.
The compact system footprint and streamlined integration may help automakers adapt to shifting radio policies.
The compact system footprint and streamlined integration may help automakers adapt to shifting radio policies.
The new registering clock driver raises registered DIMM data rates to 9,600 MT/s for CPU-based servers.
The new registering clock driver raises registered DIMM data rates to 9,600 MT/s for CPU-based servers.
Siemens’ updated Fuse EDA AI Agent validates its own decisions against deterministic, physics-based EDA engines.
Siemens’ updated Fuse EDA AI Agent validates its own decisions against deterministic, physics-based EDA engines.
In this edition of Business Shorts, SK Group and Nvidia plan $500 billion in AI infrastructure, TDK and LG Innotek team…
In this edition of Business Shorts, SK Group and Nvidia plan $500 billion in AI infrastructure, TDK and LG Innotek team up on robotic sensing, and Micron locks in automotive memory supply.
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