Latest FPGA Articles and Videos

Osaka University researchers have built a new device that can be customized by the user for maximum efficiency in AI applications.

Osaka University researchers have built a new device that can be customized by the user for maximum efficiency in AI applications.

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability…

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability verification of AI/ML processors is critical since failures can have major consequences for the validity and legitimacy of AI/ML technology.

This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of…

This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the…

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

NSITEXE utilizes Synopsys’ development tools and IP to build a SoC (system-on-a-chip) for autonomous driving.

NSITEXE utilizes Synopsys’ development tools and IP to build a SoC (system-on-a-chip) for autonomous driving.

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and…

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction…

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB,…

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

In this article, we’ll study the basic structure of a Verilog module, look at some examples of using the Verilog…

In this article, we’ll study the basic structure of a Verilog module, look at some examples of using the Verilog “wire” data type and its vector form, and briefly touch on some differences between VHDL and Verilog.

This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock…

This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock signal that will be used with an FPGA design.

This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and…

This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and function as a basic walkthrough of the Fast Fourier Transform interface.

This article will look at the techniques that Vivado employs to accelerate design implementation.

This article will look at the techniques that Vivado employs to accelerate design implementation.

This article will look at some of the most important features of the Xilinx Vivado Design Suite which accelerates the…

This article will look at some of the most important features of the Xilinx Vivado Design Suite which accelerates the "time to integration" of the design procedure.

SiFive announces an open-source SoC platform based on RISC-V and NVDLA architectures.

SiFive announces an open-source SoC platform based on RISC-V and NVDLA architectures.

This article explores some important details related to the design and functionality of processors.

This article explores some important details related to the design and functionality of processors.

This article will look at some of the consequences of adding a reset input to an FPGA design.

This article will look at some of the consequences of adding a reset input to an FPGA design.