Latest CPUs Articles and Videos

Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?

Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction…

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB,…

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

SiFive announces an open-source SoC platform based on RISC-V and NVDLA architectures.

SiFive announces an open-source SoC platform based on RISC-V and NVDLA architectures.

Continuing our series on the Instruction Set Architecture (ISA), this week we delve into the PowerPC ISA.

Continuing our series on the Instruction Set Architecture (ISA), this week we delve into the PowerPC ISA.

AAC writer, Chantelle Dubois, had a chance to speak one-on-one with the head of SiFive's DesignShare program about the…

AAC writer, Chantelle Dubois, had a chance to speak one-on-one with the head of SiFive's DesignShare program about the benefits to IP sharing, and what he believes will be important for the future of SoC design.

The catalog of IPs includes security cores, Logic NVM technology, embedded analytics, and multicore debugging toolsets.

The catalog of IPs includes security cores, Logic NVM technology, embedded analytics, and multicore debugging toolsets.

SiFive, the company behind the first RISC-V based SoCs, has recently announced the addition of Flex Logix’s FPGA IP to…

SiFive, the company behind the first RISC-V based SoCs, has recently announced the addition of Flex Logix’s FPGA IP to its DesignShare initiative.

The RISC-V Foundation has continued to build on its momentum, announcing that this month the open-source ISA presence at…

The RISC-V Foundation has continued to build on its momentum, announcing that this month the open-source ISA presence at HOT CHIPS 29.

Open source hardware met open source instruction set architecture this month when SiFive announced the Arduino…

Open source hardware met open source instruction set architecture this month when SiFive announced the Arduino Cinque—an Arduino development board based off the RISC-V ISA.

The RISC-V footprint is expanding with the commercial availability of open-source chips and related development boards…

The RISC-V footprint is expanding with the commercial availability of open-source chips and related development boards from silicon startups like SiFive and OnChip.