In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction…
In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.
This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring…
This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring systems to comply with this standard while introducing an automotive power monitor that has been certified to meet this standard.
RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.
RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.
The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.
The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.
This application note describes an SLG46140V design that implements a 16-bit up/down counter with quadrature encoder…
This application note describes an SLG46140V design that implements a 16-bit up/down counter with quadrature encoder inputs. The GreenPAK device relieves the host of real-time input requirements and allows for easy connection of multiple encoders.
This application note describes a simple hardware implementation of a 4-Mux LCD driver using time division multiplexing…
This application note describes a simple hardware implementation of a 4-Mux LCD driver using time division multiplexing techniques along with system monitoring using a GreenPAK IC.
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.
This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed…
This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.
This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and…
This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.
Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction…
Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.
In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold…
In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold increase in performance with up to a 70% energy savings per bit compared to DDR3 DRAM.
What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture?…
What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.
This article explores the pros and cons of either designing embedded systems from scratch or utilizing pre-made…
This article explores the pros and cons of either designing embedded systems from scratch or utilizing pre-made single-board computers.
This article explores the pros and cons of connectivity options for IoT edge device design.
This article explores the pros and cons of connectivity options for IoT edge device design.
This article explores the equal importance of software and hardware security for IoT devices and provides actionable…
This article explores the equal importance of software and hardware security for IoT devices and provides actionable steps for securing embedded processors on RISC-V.
This article provides an overview of what an IoT node needs for a faster and simpler implementation of robust security.
This article provides an overview of what an IoT node needs for a faster and simpler implementation of robust security.
This video demonstrates how to set up and use ROHM's sensor evaluation kit for IoT for prototyping and testing new IoT devices.
This video demonstrates how to set up and use ROHM's sensor evaluation kit for IoT for prototyping and testing new IoT devices.
RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for…
RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for this technology.