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The Journey of RISC-V Implementation

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.


Meeting ASIL Compliance for ADAS with an Integrated SoC Power System Monitor

Meeting ASIL Compliance for ADAS with an Integrated SoC Power System Monitor

This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring systems to comply with this standard while introducing an automotive power monitor that has been certified to meet this standard.


RISC-V’s Role in Securing IoT-Connected Devices

RISC-V’s Role in Securing IoT-Connected Devices

RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.


Adding Custom Instructions to RISC-V to Boost Performance While Reducing Power and Code Density

Adding Custom Instructions to RISC-V to Boost Performance While Reducing Power and Code Density

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.


An Introduction to SweRV, a RISC-V Core

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.


Designing a Quadrature Encoder Counter with an SPI Bus

Designing a Quadrature Encoder Counter with an SPI Bus

This application note describes an SLG46140V design that implements a 16-bit up/down counter with quadrature encoder inputs. The GreenPAK device relieves the host of real-time input requirements and allows for easy connection of multiple encoders.


Designing a System Monitor 4-MUX LCD Driver Solution

Designing a System Monitor 4-MUX LCD Driver Solution

This application note describes a simple hardware implementation of a 4-Mux LCD driver using time division multiplexing techniques along with system monitoring using a GreenPAK IC.


Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.


Keeping RISC-V-Based Embedded System Design Flexible with Linux and Zephyr microPlatforms

Keeping RISC-V-Based Embedded System Design Flexible with Linux and Zephyr microPlatforms

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.


Running Hard Real-Time Applications and Linux on PolarFire SoC

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.


How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.


CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.


Hybrid Memory Cubes: What They Are and How They Work

Hybrid Memory Cubes: What They Are and How They Work

In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold increase in performance with up to a 70% energy savings per bit compared to DDR3 DRAM.


Building Out the RISC-V Ecosystem

Building Out the RISC-V Ecosystem

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.


Embedded System Design: Build from Scratch or Use an SBC?

Embedded System Design: Build from Scratch or Use an SBC?

This article explores the pros and cons of either designing embedded systems from scratch or utilizing pre-made single-board computers.


Utilizing the Different Types of Common IoT Connection Methods

Utilizing the Different Types of Common IoT Connection Methods

This article explores the pros and cons of connectivity options for IoT edge device design.


Securing Embedded Processors on RISC-V

Securing Embedded Processors on RISC-V

This article explores the equal importance of software and hardware security for IoT devices and provides actionable steps for securing embedded processors on RISC-V.


Simplifying Hardware Security Implementation for IoT Nodes

Simplifying Hardware Security Implementation for IoT Nodes

This article provides an overview of what an IoT node needs for a faster and simpler implementation of robust security.


How to Set Up ROHM’s Arduino Sensor Shield for IoT | AAC How-To

How to Set Up ROHM’s Arduino Sensor Shield for IoT | AAC How-To

This video demonstrates how to set up and use ROHM's sensor evaluation kit for IoT for prototyping and testing new IoT devices.


RISC-V: All Hype or Real Hope for the Processor Market?

RISC-V: All Hype or Real Hope for the Processor Market?

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for this technology.