Latest IC Design Industry Articles

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks…

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

See how multi-channel automotive LED driver ICs implement backlight local dimming, bringing ‘true black’ to…

See how multi-channel automotive LED driver ICs implement backlight local dimming, bringing ‘true black’ to automotive LCD displays.

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability…

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability verification of AI/ML processors is critical since failures can have major consequences for the validity and legitimacy of AI/ML technology.

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the…

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

This article describes a methodology that automates set up, constraints, and results analysis as designs move from static…

This article describes a methodology that automates set up, constraints, and results analysis as designs move from static CDC analysis to formal verification to simulation and avoid manual scripting efforts, thus reducing setup effort and errors.

This article discusses the issues surrounding trace-width calculation and provides a solid foundation for designing your…

This article discusses the issues surrounding trace-width calculation and provides a solid foundation for designing your next high-current net.

This article introduces and explores advanced ERC, highlighting its differences from traditional ERC and discussing how…

This article introduces and explores advanced ERC, highlighting its differences from traditional ERC and discussing how it can help create better circuit designs.

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when…

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring…

This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring systems to comply with this standard while introducing an automotive power monitor that has been certified to meet this standard.

RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.

RISC-V hardware offers additional security for IoT-connected embedded devices beyond software cybersecurity.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

Novel approaches to end node power supply design using switched-mode converters can enable a wireless end node to operate…

Novel approaches to end node power supply design using switched-mode converters can enable a wireless end node to operate from a CR2032 lithium coin cell with up to +20 dBm transmit power.

This article explores the challenge of constantly powering the billions of devices that make up the IoT and how energy…

This article explores the challenge of constantly powering the billions of devices that make up the IoT and how energy harvesting could be an effective solution.

This article presents the challenges of powering a digital camera and proposes a new design approach to save power while…

This article presents the challenges of powering a digital camera and proposes a new design approach to save power while being more flexible.

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed…

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

In this article, we will look at the characteristics of the SiC JFET and how these characteristics are suited for circuit…

In this article, we will look at the characteristics of the SiC JFET and how these characteristics are suited for circuit protection applications.