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An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

May 14, 2019 by Zvonimir Bandić, Western Digital

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

April 16, 2019 by Greg Sullivan, Dover Microsystems

Keeping RISC-V-Based Embedded System Design Flexible with Linux and Zephyr microPlatforms

This article discusses Foundries.io's microPlatforms which support Intel, Arm, and RISC-V architectures and are designed to avoid lock-in to specific hardware implementations.

March 28, 2019 by Trina Watt, Foundries.io

Running Hard Real-Time Applications and Linux on PolarFire SoC

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

March 26, 2019 by Tim Morin, Microchip

Utilizing SiC JFETs in Circuit Protection Applications

In this article, we will look at the characteristics of the SiC JFET and how these characteristics are suited for circuit protection applications.

March 21, 2019 by Anup Bhalla, UnitedSiC

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

March 20, 2019 by Ted Marena, Western Digital

How to Utilize the RISC-V Instruction Set CKB-VM

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

March 19, 2019 by Xuejie Xiao, Nervos

CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

March 12, 2019 by Xuejie Xiao, Nervos

Introduction to the RISC-V Instruction Set CKB-VM and its Requirements

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

March 05, 2019 by Xuejie Xiao, Nervos

Bel Fuse Circuit Protection 0AD Series Family of Fuses

The Bel Fuse 0AD family of fuses are small fuses with very high AC and DC voltage ratings and interrupting ratings. The fuses leverage advanced materials and processing to shrink the fuse size without sacrificing electrical performance or physical integrity.

February 01, 2019 by Bel Fuse

How Do I Prep My PCB for Fabrication? Accelerating PCB Assembly with Design Best Practices

In this article, Parker Dillman, lead EE and co-founder of MacroFab, covers how to best prepare your PCB designs for fabrication and assembly.

January 15, 2019 by Parker Dillmann, MacroFab

Building Out the RISC-V Ecosystem

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.

December 20, 2018 by Markus Levy, NXP Semiconductors

Designing Smart Meters with Circuit Protection, Sensing, and Power Control Capabilities

This article offers an overview of the various component options for smart meter design and how they can improve the operation of the meters into which they are designed.

December 04, 2018 by Philippe Di Fulvio, Littelfuse Inc

Embedded System Design: Build from Scratch or Use an SBC?

This article explores the pros and cons of either designing embedded systems from scratch or utilizing pre-made single-board computers.

November 29, 2018 by Rudy Ramos, Mouser

Securing Embedded Processors on RISC-V

This article explores the equal importance of software and hardware security for IoT devices and provides actionable steps for securing embedded processors on RISC-V.

October 31, 2018 by Dan Ganousis, Dover Microsystems

Resolving the Signal Part 9: Reducing Reference Noise in High-Resolution Delta-Sigma ADC Circuits

Part 9 of the Resolving the Signal series analyzes several different methods for reducing reference noise's effect in systems and examines the difference of reference noise's impact on low- and high-resolution ADCs.

October 02, 2018 by Bryan Lizon, Texas Instruments

RISC-V: All Hype or Real Hope for the Processor Market?

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for this technology.

September 18, 2018 by Jothy Rosenberg, Dover Microsystems

Resolving the Signal Part 8: How Voltage Reference Noise Affects Delta Sigma ADCs

Part 8 of the Resolving the Signal series dives further into how different noise sources impact precision delta-sigma ADCs by focusing on reference noise and ADC noise, and how gain affects reference noise.

August 21, 2018 by Bryan Lizon, Texas Instruments

Utilizing Open Source Hardware in Academic Environments

In this article, the author explores and explains his team's process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment.

August 08, 2018 by Frank K. Gürkaynak, ETH Zurich

Evaluating the Robustness of 1200 V SiC MOSFETs Under Short Circuit Conditions

Are SiC MOSFETs the best answer for maximizing a power converter's efficiency? This article explores a recent study performed on a 1200 V, 80 mΩ SiC MOSFET, highlighting its short circuit capabilities.

July 16, 2018 by Littelfuse, Inc