Latest Softcore Articles and Videos

Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.

Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.

Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that…

Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the…

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

In this article, we’ll first review the basic architecture of a SAR ADC and then take a look at one of its common applications.

In this article, we’ll first review the basic architecture of a SAR ADC and then take a look at one of its common applications.

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when…

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

Alibaba is set to produce the next generation of Chinese processors with the RISC-V instead of Arm architecture.

Alibaba is set to produce the next generation of Chinese processors with the RISC-V instead of Arm architecture.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.

This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.

Learn more about the Arm computer architecture, including ISA, execution states, and processor families.

Learn more about the Arm computer architecture, including ISA, execution states, and processor families.

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…

This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.

In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the…

In this article we’ll look at the defining characteristics of these extremely popular ICs, and then we’ll explore the internal architecture.

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and…

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction…

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

Can IoT devices handle edge processing for machine learning and DSP? Arm's newly-announced Helium vector extension for…

Can IoT devices handle edge processing for machine learning and DSP? Arm's newly-announced Helium vector extension for Cortex-M processors aims to facilitate more complex development on the edge.

Learn about the microarchitecture of an ARM processor, including an explanation of the register file and how it functions…

Learn about the microarchitecture of an ARM processor, including an explanation of the register file and how it functions within a processor.

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture?…

What is an ecosystem and what is not? How does the term ecosystem apply to RISC-V and it's open-source architecture? Markus Levy nad Robert Oshana weigh in on RISC-V as an ecosystem, where that ecosystem is today, and discusses new developments in RISC-V.

Is open source changing the way we manage data? Western Digital, a data storage device company, switched to RISC-V's…

Is open source changing the way we manage data? Western Digital, a data storage device company, switched to RISC-V's open-source ISA (instruction set architecture) a year ago. This month, they announced a series of open-source, collaborative initiatives that aim to make data more open, from processor cores to memory caches.