This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of…
This New Product Brief (NPB) is part of a video series highlighting the features, applications, and technical specs of newly-released products.
As the co-founders of RISC-V, SiFive's level-up on processors could have significant implications for custom SoC design.
As the co-founders of RISC-V, SiFive's level-up on processors could have significant implications for custom SoC design.
Laser frequency combs small enough to fit on an IC have significant implications for frequency measurement and communications.
Laser frequency combs small enough to fit on an IC have significant implications for frequency measurement and communications.
Recently, a study into the architecture has been presented by members of the Wireless Networking and AI&ML research…
Recently, a study into the architecture has been presented by members of the Wireless Networking and AI&ML research groups and described as a “new standard” for telecommunications networks.
The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.
The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.
Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.
Microchip's new RISC-V-based PolarFire SoC family is said to provide 50% lower power than competing mid-range FPGAs.
Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that…
Groq, a semiconductor startup with software roots, has developed a new processing unit with a unique architecture that offers inference solutions for AI acceleration.
In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when…
In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.
This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.
This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.
Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?
Will open source hardware become as ubiquitous as open-source software, such as Linux and Android?
This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up…
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral…
In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.
Learn more about the Arm computer architecture, including ISA, execution states, and processor families.
Learn more about the Arm computer architecture, including ISA, execution states, and processor families.
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications…
This article discusses the RISC-V-based SoC FPGA architecture for PolarFire SoC, which allows hard real-time applications and Linux applications to coexist.
This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and…
This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.
The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB,…
The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.
Can IoT devices handle edge processing for machine learning and DSP? Arm's newly-announced Helium vector extension for…
Can IoT devices handle edge processing for machine learning and DSP? Arm's newly-announced Helium vector extension for Cortex-M processors aims to facilitate more complex development on the edge.
Is open source changing the way we manage data? Western Digital, a data storage device company, switched to RISC-V's…
Is open source changing the way we manage data? Western Digital, a data storage device company, switched to RISC-V's open-source ISA (instruction set architecture) a year ago. This month, they announced a series of open-source, collaborative initiatives that aim to make data more open, from processor cores to memory caches.
Facebook
Google
GitHub
Linkedin