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How RISC-V Security Stacks Strengthen Computer Architecture

How RISC-V Security Stacks Strengthen Computer Architecture

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.


How Automated CDC Protocol Verification Accelerates Testing Processes

How Automated CDC Protocol Verification Accelerates Testing Processes

This article describes a methodology that automates set up, constraints, and results analysis as designs move from static CDC analysis to formal verification to simulation and avoid manual scripting efforts, thus reducing setup effort and errors.


The Importance of Advanced ERC in Circuit Design

The Importance of Advanced ERC in Circuit Design

This article introduces and explores advanced ERC, highlighting its differences from traditional ERC and discussing how it can help create better circuit designs.


The Journey of RISC-V Implementation

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.


Meeting ASIL Compliance for ADAS with an Integrated SoC Power System Monitor

Meeting ASIL Compliance for ADAS with an Integrated SoC Power System Monitor

This article looks at the safety standard that governs ADAS features and the challenge in designing power monitoring systems to comply with this standard while introducing an automotive power monitor that has been certified to meet this standard.


Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.


An Introduction to SweRV, a RISC-V Core

An Introduction to SweRV, a RISC-V Core

This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.


Designing a Quadrature Encoder Counter with an SPI Bus

Designing a Quadrature Encoder Counter with an SPI Bus

This application note describes an SLG46140V design that implements a 16-bit up/down counter with quadrature encoder inputs. The GreenPAK device relieves the host of real-time input requirements and allows for easy connection of multiple encoders.


Designing a System Monitor 4-MUX LCD Driver Solution

Designing a System Monitor 4-MUX LCD Driver Solution

This application note describes a simple hardware implementation of a 4-Mux LCD driver using time division multiplexing techniques along with system monitoring using a GreenPAK IC.


Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

Decreasing the Length of Design Cycle in Co-Designed SoCs with Renode

In this article, we explain how the use of open-source functional simulators like Antmicro’s Renode can be an integral part of hardware-software co-design efforts.


Improving Temperature Sensor Accuracy for Thermocouples and RTDs with Delta-Sigma Converters

Improving Temperature Sensor Accuracy for Thermocouples and RTDs with Delta-Sigma Converters

This design solution evaluates the accuracy of thermocouples used for high-temperature measurements as well as resistance temperature detectors (RTDs) used for local cold-junction-compensation (CJC) points.


How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.


Hybrid Memory Cubes: What They Are and How They Work

Hybrid Memory Cubes: What They Are and How They Work

In this article, the engineering team at Promwad examines hybrid memory cubes (HMCs), which can provide a 15-fold increase in performance with up to a 70% energy savings per bit compared to DDR3 DRAM.


RISC-V: All Hype or Real Hope for the Processor Market?

RISC-V: All Hype or Real Hope for the Processor Market?

RISC-V is changing processor design through open source hardware. In this article, learn about some of the new uses for this technology.


Measure Position and Speed Control of a DC Motor Using an Analog PID Controller

Measure Position and Speed Control of a DC Motor Using an Analog PID Controller

This article shows how to implement an analog PID controller, including adjusting of the angular position of a DC motor shaft, editing the design to control its speed, and tuning PID parameters for reliable performance.


Build a PWM Controller for PC Fans with GreenPAK

Build a PWM Controller for PC Fans with GreenPAK

This article shows how to build a 12 V PC fan PWM controller with GreenPAK ICs.


3-Phase Brushless DC Motor Control with Hall Sensors

3-Phase Brushless DC Motor Control with Hall Sensors

This article describes how to control a 3-phase brushless DC motor using a GreenPAK.


Implementing a Binary Parity Generator and Checker with GreenPAK

Implementing a Binary Parity Generator and Checker with GreenPAK

This app note implements a binary parity generator and checker with two data input variants, a parallel data input, and a serial data input. It describes the implemented logic, GreenPAKs implementation, and the obtained results.


Making the Cloud More Powerful: Xilinx FPGAs and Adaptive Workload Acceleration

Making the Cloud More Powerful: Xilinx FPGAs and Adaptive Workload Acceleration

Historically, FPGAs have been challenging to work with. To combat that reputation, Xilinx developed programmable devices that simplify—and accelerate—the implementation of customized hardware development.


Side-Wettable Flanks Enable AOI on Leadless SMD (DFN) Packages

Side-Wettable Flanks Enable AOI on Leadless SMD (DFN) Packages

Quad flat no-lead and discrete (or dual) flat no-lead packages provide a welcome increase in component density on a PCB area by eliminating leads. However, the solder connection quality cannot be tested by automated optical inspection. This article explores solutions to this often costly problem.