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In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts…

In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts off-the-shelf FPGA servers into high-efficiency AI inference engines.

Learn how monolithic ceramic cooling using Selective Laser Reaction Sintering (SLRS) eliminates the "thermal wall" in…

Learn how monolithic ceramic cooling using Selective Laser Reaction Sintering (SLRS) eliminates the "thermal wall" in high-density power electronics by creating single-piece, reliable heat exchangers.

Learn how GaN technology enables a low-cost, low-profile 6 kW, 800 VDC to 12.5 VDC converter using an ISOP LLC topology.…

Learn how GaN technology enables a low-cost, low-profile 6 kW, 800 VDC to 12.5 VDC converter using an ISOP LLC topology. This meets the design needs of next-gen, MW-scale AI server infrastructure.

Optical computing is the "New Moore's Law" for AI. It solves electronic scaling limits, offering higher speed, lower…

Optical computing is the "New Moore's Law" for AI. It solves electronic scaling limits, offering higher speed, lower power, and efficiency gains proportional to problem size for matrix operations.

Learn why the best silicon is useless without the right AI developer tools.

Learn why the best silicon is useless without the right AI developer tools.

In the final part of this series, we zero in on three photonics technologies expected to be essential for demanding…

In the final part of this series, we zero in on three photonics technologies expected to be essential for demanding computing and communication systems of the future.

Announced today, Broadcom’s Gen 8 128G Fibre Channel switch portfolio is claimed as the first quantum-safe, SAN…

Announced today, Broadcom’s Gen 8 128G Fibre Channel switch portfolio is claimed as the first quantum-safe, SAN architecture with 128G speed, AI-powered SAN management, and quantum-safe cryptography.

Learn how to solve QLC NAND's endurance, ECC, and performance issues for hyperscale. The approach blends a PCIe Gen5…

Learn how to solve QLC NAND's endurance, ECC, and performance issues for hyperscale. The approach blends a PCIe Gen5 controller with hardware-accelerated LDPC, PerformaShape QoS, and more.

We examine the software used in a 2025 object detection demo and the lessons it holds for developing new edge AI products.

We examine the software used in a 2025 object detection demo and the lessons it holds for developing new edge AI products.

Learn how “right-sized” machine learning enables edge devices to make critical decisions locally, improving…

Learn how “right-sized” machine learning enables edge devices to make critical decisions locally, improving reliability and reducing reliance on cloud connectivity in remote, volatile environments.

The design features wide bandgap semiconductors in a full-bridge LLC with planar magnetics.

The design features wide bandgap semiconductors in a full-bridge LLC with planar magnetics.

The new Akida Cloud is developed for instant access to the company's innovations and reduced development cycles.

The new Akida Cloud is developed for instant access to the company's innovations and reduced development cycles.

Learn how UALink offers an open, high-speed interconnect for AI accelerators, that enables scalable, low-latency, and…

Learn how UALink offers an open, high-speed interconnect for AI accelerators, that enables scalable, low-latency, and energy-efficient AI systems for next-gen workloads.

With its E1 processor announced today, Efficient Computer is hoping to usher in a new era of general-purpose computing efficiency.

With its E1 processor announced today, Efficient Computer is hoping to usher in a new era of general-purpose computing efficiency.

Hailo-10H launch arrives as the edge AI accelerator market is projected to grow from $10.13 billion in 2025 to $113.71…

Hailo-10H launch arrives as the edge AI accelerator market is projected to grow from $10.13 billion in 2025 to $113.71 billion by 2034, driven by the demand for privacy-first, low-latency AI processing.

Unveiled today, the new timing chips from Mixed-Signal Devices offer 2 GHz performance and use scalable CMOS to overcome…

Unveiled today, the new timing chips from Mixed-Signal Devices offer 2 GHz performance and use scalable CMOS to overcome the limits of analog alternatives.

Announced today, the high-performance switch IC enables scale-up and scale-out for AI networks and supports co-packaged optics.

Announced today, the high-performance switch IC enables scale-up and scale-out for AI networks and supports co-packaged optics.

Both copper and optical interconnects face limitations as choices for next gen data centers. Learn how a third option…

Both copper and optical interconnects face limitations as choices for next gen data centers. Learn how a third option promises to enable scaling up AI clusters in data centers for years to come.

In this exclusive Embedded World 2025 interview, we talk to AMD’s Kirk Saban about edge AI, ASICs vs. FPGAs, Adaptive…

In this exclusive Embedded World 2025 interview, we talk to AMD’s Kirk Saban about edge AI, ASICs vs. FPGAs, Adaptive SoCs, embedded x86, and the outlook ahead.