The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI I/O, and robust security/reliability…
The Titanium Edge FPGA family targets constrained edge AI with 50% lower power, compact SiP packages, high-speed MIPI I/O, and robust security/reliability features for intelligent systems.
The ST54M places an NFC controller, secure element, and eSIM on one die and adds a hardware accelerator for NIST's…
The ST54M places an NFC controller, secure element, and eSIM on one die and adds a hardware accelerator for NIST's post-quantum algorithms.
IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion…
IBM leveraged its nanostack architecture, a technique that "builds a chip like a city," to pack nearly 100 billion transistors on a fingernail-sized chip.
The new 8-GHz active differential probe and vector signal analysis software target PCIe, DDR, USB, Ethernet, Wi-Fi, LTE,…
The new 8-GHz active differential probe and vector signal analysis software target PCIe, DDR, USB, Ethernet, Wi-Fi, LTE, and 5G signal analysis.
Four deals target edge AI hardware and software, data center cooling, and embedded development tools.
Four deals target edge AI hardware and software, data center cooling, and embedded development tools.
The 60 V and 100 V parts pair low on-resistance with small footprints as industrial systems migrate from 12 V and 24V…
The 60 V and 100 V parts pair low on-resistance with small footprints as industrial systems migrate from 12 V and 24V rails toward 48 V distribution.
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and…
The OECD is analyzing the semiconductor industry, focusing on supply chain resilience, global value chain mapping, and the impact of rising industrial subsidies on global market competition.
The PicoScope 5000E Series delivers a 22-µV RMS noise floor and up to 5-GS/s sampling in a USB-C-powered package.
The PicoScope 5000E Series delivers a 22-µV RMS noise floor and up to 5-GS/s sampling in a USB-C-powered package.
Called Gleanmer, the 16-nm system-on-chip swaps memory-hungry voxels for compact Gaussian “blobs” to map and navigate…
Called Gleanmer, the 16-nm system-on-chip swaps memory-hungry voxels for compact Gaussian “blobs” to map and navigate at roughly 6 mW.
U-blox has introduced the MAYA-W5 and NORA-W5 Wi-Fi 6 module families for industrial and IoT applications, designed and…
U-blox has introduced the MAYA-W5 and NORA-W5 Wi-Fi 6 module families for industrial and IoT applications, designed and manufactured in Europe.
The full-stack platform pairs the IGX Thor compute module with a safety-certified software stack and an accredited…
The full-stack platform pairs the IGX Thor compute module with a safety-certified software stack and an accredited inspection lab, with humanoid maker Agility as the first adopter.
The 33-mm, coin-cell-powered board includes dual antennas, multiprotocol wireless support, and an integrated sensor suite.
The 33-mm, coin-cell-powered board includes dual antennas, multiprotocol wireless support, and an integrated sensor suite.
Intel's 1980 microcontroller put a CPU, memory, timers, and serial I/O on a single chip. It’s an architecture that…
Intel's 1980 microcontroller put a CPU, memory, timers, and serial I/O on a single chip. It’s an architecture that still ships inside billions of devices.
The programmable Hall switch can detect up to four positions using a single device.
The programmable Hall switch can detect up to four positions using a single device.
OpenAI and Broadcom unveiled Jalapeño, OpenAI’s first custom AI accelerator designed from scratch for LLM inference,…
OpenAI and Broadcom unveiled Jalapeño, OpenAI’s first custom AI accelerator designed from scratch for LLM inference, developed from initial design to tape-out in 9 months.
Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts…
Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts board space by 60% while gaining 288 GB/s bandwidth and 15-year lifecycle.
Launched today, Synopsys’ ESUN IP solution slashes AI tail latency and eliminates networking bottlenecks to enable…
Launched today, Synopsys’ ESUN IP solution slashes AI tail latency and eliminates networking bottlenecks to enable seamless, scalable performance for modern AI infrastructure.
The new system-on-chip pairs a heterogeneous AI compute engine with a low-latency multi-camera image signal processor,…
The new system-on-chip pairs a heterogeneous AI compute engine with a low-latency multi-camera image signal processor, and can ship pre-integrated with emotion3D perception software.
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language…
The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language models at lower cost per token.
The new reference design leverages EPC’s monolithic GaN module to deliver an ultra-compact, high-efficiency motor drive…
The new reference design leverages EPC’s monolithic GaN module to deliver an ultra-compact, high-efficiency motor drive solution specifically optimized for humanoid robotics and drones.
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