Latest FPGA Technical Articles

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The Fundamentals of Time-Sensitive Networking

Learn about the benefits of time-sensitive networking (TSN) and how engineers use it to ensure that an industrial system is ready for the future. This article focuses on three members of the set of TSN standards.

January 19, 2021 by Jeff Steinheider, NXP Semiconductors

Which Encoding Type Should I Use? Example FPGA Applications

Follow three experiments that show the process of determining which kind of encoding suits a given FPGA.

January 06, 2021 by Eduardo Corpeño

Comparing Binary, Gray, and One-Hot Encoding

This article shows a comparison of the implementations that result from using binary, Gray, and one-hot encodings to implement state machines in an FPGA. These encodings are often evaluated and applied by the synthesis and implementation tools, so it’s important to know why the software makes these decisions.

January 05, 2021 by Eduardo Corpeño

JTAG Implementation in Arm Core Devices

This article will teach you about the intersection between JTAG and Arm core devices, with special attention paid to the Arm Debug Interface or ADI.

December 14, 2020 by Sam Gallagher

JTAG Connectors and Interfaces

Learn about the interfaces and connectors used to implement JTAG.

November 23, 2020 by Sam Gallagher

The JTAG Test Access Port (TAP) State Machine

In this article, we’re going to look at the test access state machine in detail and even see some pseudocode for a simple JTAG interface.

November 20, 2020 by Sam Gallagher

Introduction to JTAG and the Test Access Port (TAP)

In this article, we’re going to be talking about JTAG, the ubiquitous hardware tool used for testing, programming, and debugging.

November 18, 2020 by Sam Gallagher

Protecting IoT Embedded Designs with Security ICs

In this article, we discuss some key security threats to be aware of when designing for the IoT, important security functions, and how protecting these designs is becoming easier with advances in security ICs. 

September 15, 2020 by Scott Jones, Maxim Integrated

How to Obtain the Temperature Value from a Thermistor Measurement

This article explains how to use an NTC or a PTC thermistor with an ADC, along with the various process techniques to convert ADC measured results into a usable temperature value.

August 18, 2020 by Gordon Varney, Texas Instruments

An Example of Securing In-Cabin AI using TEE on a Secure FPGA SoC

This article discusses trusted execution environments — already used in a variety of connected devices — by showing how using TEE and an FPGA SoC can work in vehicle in-cabin AI.

July 28, 2020 by Katherine Hsu, Hex-Five Security

What Is a Hardware Description Language (HDL)?

This FEQ (or Frequent Engineering Question) covers the basics of a crucial topic: hardware description languages.

March 11, 2020 by Robert Keim

Watchdog Timers in Microcontrollers

This article is the fourth of a series on microcontroller timers which discusses internal watchdogs.

February 10, 2020 by Stephen Colley

Real Time Clocks (RTCs) in Microcontroller Timers

This article is the third of a series on microcontroller timers which describes the RTCs inside a microcontroller.

February 09, 2020 by Stephen Colley

Introduction to Microcontroller Timers: Periodic Timers

This article, the first in a series on “timer/counter” functions in microcontrollers, discusses periodic timers.

January 14, 2020 by Stephen Colley

Concurrency and Interrupts in Microcontrollers and Embedded Systems

This article introduces the idea of concurrency and a mechanism that many computers provide for dealing with concurrency called interrupts.

September 30, 2019 by Philip Asare

Embedded Firmware Tips: How to Initialize Arrays in C with Signal Waveforms and Other File Data

This article shows how to initialize arrays in a C program with values from text files.

September 25, 2019 by Stephen Colley

Embedded Firmware Tips and Tricks: Use Your Read Only Memory to Free Up RAM

Learn how to use code memory to free up RAM on your MCU.

September 16, 2019 by Robert Keim

The Journey of RISC-V Implementation

In this article, Western Digital's Ted Marena explores the reasons companies have and the process they go through when integrating the open process instruction set architecture RISC-V.

September 10, 2019 by Ted Marena, Western Digital

Understanding Verilog Shift Registers

This article will discuss how to implement a shift register in Verilog. The register described can be synthesized and downloaded to an FPGA for test in actual hardware.

August 27, 2019 by Garrett Holthaus

Adding Custom Instructions to RISC-V to Boost Performance While Reducing Power and Code Density

The article discusses the benefits of a custom instruction for RISC-V and introduces the ACE framework.

June 20, 2019 by Tommy Lin, Andes Technology