An RTL glitch in an eFuse controller can permanently brick costly silicon. This article covers defense-in-depth FSM design, redundant watchdogs, and formal SVA…
An RTL glitch in an eFuse controller can permanently brick costly silicon. This article covers defense-in-depth FSM design, redundant watchdogs, and formal SVA verification.
The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article…
The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this time-consuming process using automation.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
This article demonstrates the operation of an LTspice shift register and discusses details of its schematic and timing…
This article demonstrates the operation of an LTspice shift register and discusses details of its schematic and timing relationships.
We explore the design and functionality of a digital shift register intended for use in mixed-signal circuit simulations.
We explore the design and functionality of a digital shift register intended for use in mixed-signal circuit simulations.
Customizing the device parameters of LTspice's logic gates and flip-flops can help you more accurately simulate these…
Customizing the device parameters of LTspice's logic gates and flip-flops can help you more accurately simulate these components. This article walks through the specification process and provides some helpful tips.
This article explains how to successfully integrate logic gates into an LTspice simulation.
This article explains how to successfully integrate logic gates into an LTspice simulation.
In this article, we use a SPICE model for 90 nm CMOS to plot key electrical relationships of an NMOS transistor.
In this article, we use a SPICE model for 90 nm CMOS to plot key electrical relationships of an NMOS transistor.
Current briefly flows through both transistors during logic-level transitions. This article explores the resulting power…
Current briefly flows through both transistors during logic-level transitions. This article explores the resulting power dissipation and provides some helpful LTspice tips for measuring current and power.
Learn how undervoltage lockout (UVLO) can protect semiconductor devices and electronic systems from potentially hazardous…
Learn how undervoltage lockout (UVLO) can protect semiconductor devices and electronic systems from potentially hazardous operation.
Continuing our in-depth look at a simple SPICE circuit that can generate a negative supply voltage, we’ll consider the…
Continuing our in-depth look at a simple SPICE circuit that can generate a negative supply voltage, we’ll consider the effect of oscillator frequency on the system’s performance parameters.
Indispensable for modern electrical engineering, application-specific integrated circuits (ASICs) form a diverse group of…
Indispensable for modern electrical engineering, application-specific integrated circuits (ASICs) form a diverse group of integrated circuits (ICs) that help designers to optimize sophisticated electronic devices.
Learn about the self-calibration or internal calibration function in an analog-to-digital converter (ADC).
Learn about the self-calibration or internal calibration function in an analog-to-digital converter (ADC).
This article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical…
This article is a primer into the basics of RISC-V. The open architecture philosophy is exposed, along with a technical description of the modular ISA, and some commercial RISC-V microprocessor implementations.
This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.
This article will explore AXI interconnects, the digital logic that allows multiple AXI masters and AXI slaves to communicate.
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso…
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso Periodic Steady State (PSS) analysis.
The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.
The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.
Miller capacitance is commonly used in a method for operational amplifier frequency compensation.
Miller capacitance is commonly used in a method for operational amplifier frequency compensation.
In this article, we'll discuss how shunt capacitance can be used to achieve frequency compensation in op-amps and we'll…
In this article, we'll discuss how shunt capacitance can be used to achieve frequency compensation in op-amps and we'll also see why this is not the preferred technique.
The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and…
The current mirror is an important analog building block that finds application in such diverse areas as DC biasing and current-mode signal processing.