In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
Learn how to implement finite-state machines in VHDL by creating a 4-bit binary counter. After compiling, it will run on…
Learn how to implement finite-state machines in VHDL by creating a 4-bit binary counter. After compiling, it will run on an Altera CPLD development board connected to a custom PCB with input switches and an LED display.
This article covers undesired switching events, known as hazards, that can occur when developing combinational logic circuits.
This article covers undesired switching events, known as hazards, that can occur when developing combinational logic circuits.
Gate-level implementation of logic functions is limited by the gate fan-in. This article examines logic factoring,…
Gate-level implementation of logic functions is limited by the gate fan-in. This article examines logic factoring, grouping, and level increases to implement logic functions with limited input gates.
This article launches a series exploring the question of how to model data converters for system simulations.
This article launches a series exploring the question of how to model data converters for system simulations.
This article shows a comparison of the implementations that result from using binary, Gray, and one-hot encodings to…
This article shows a comparison of the implementations that result from using binary, Gray, and one-hot encodings to implement state machines in an FPGA. These encodings are often evaluated and applied by the synthesis and implementation tools, so it’s important to know why the software makes these decisions.
This article discusses the use of finite state machines (or FSMs) in design, including the initial state and the way…
This article discusses the use of finite state machines (or FSMs) in design, including the initial state and the way memory configuration affects FPGA design.
This article describes the basics of finite state machines and shows a practical way of implementing them in the Verilog…
This article describes the basics of finite state machines and shows a practical way of implementing them in the Verilog Hardware Description Language.
Learn the high-level overview of digital integrated circuit (IC) design.
Learn the high-level overview of digital integrated circuit (IC) design.
This FEQ (or Frequent Engineering Question) covers the basics of a crucial topic: hardware description languages.
This FEQ (or Frequent Engineering Question) covers the basics of a crucial topic: hardware description languages.
Learn how simulating a voltage buffer can help you implement it more effectively to boost the output current drive of an op-amp.
Learn how simulating a voltage buffer can help you implement it more effectively to boost the output current drive of an op-amp.
In this entry of our Frequent Engineering Questions (FEQ) series, learn the basics of how a load line can be used in…
In this entry of our Frequent Engineering Questions (FEQ) series, learn the basics of how a load line can be used in designing circuits.
In this article, we’ll perform some classification experiments and gather data on the relationship between hidden-layer…
In this article, we’ll perform some classification experiments and gather data on the relationship between hidden-layer dimensionality and network performance.
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso…
Learn a method of attaining convergence when simulating very high Q crystal oscillators using Cadence’s Virtuoso Periodic Steady State (PSS) analysis.
This article looks at the common options for a four-layer board stackup.
This article looks at the common options for a four-layer board stackup.
This article will discuss how to implement a shift register in Verilog. The register described can be synthesized and…
This article will discuss how to implement a shift register in Verilog. The register described can be synthesized and downloaded to an FPGA for test in actual hardware.
Learn how to use the gridded ground technique to reduce noise in a double-sided PCB.
Learn how to use the gridded ground technique to reduce noise in a double-sided PCB.
Learn best layout practices for your DC-DC buck converter circuits.
Learn best layout practices for your DC-DC buck converter circuits.
Learn how to measure noise using LTspice for op-amp circuits with handy examples.
Learn how to measure noise using LTspice for op-amp circuits with handy examples.
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