Latest FPGA Technical Articles

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What Is Mixed-Signal IC Design?

This brief gives an overview of the steps in a typical mixed-signal IC design flow.

December 07, 2020 by Jean-Jacques DeLisle

What Is Digital IC Design?

Learn the high-level overview of digital integrated circuit (IC) design.

December 02, 2020 by Jean-Jacques DeLisle

The Importance of Reliability Verification in AI/ML Processors

With the adoption of artificial intelligence and machine learning in a wide variety of applications, reliability verification of AI/ML processors is critical since failures can have major consequences for the validity and legitimacy of AI/ML technology.

January 21, 2020 by Neel Natekar, Mentor

How RISC-V Security Stacks Strengthen Computer Architecture

In this article, Ted Speers of Microchip reflects on how RISC-V and its security stack offer a solution for the development of computer architecture and processor security.

November 26, 2019 by Ted Speers, Microchip

IC Design Resources Roundup: Mentor, Cadence, and Synopsys

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.

August 05, 2019 by Gary Elinoff

Open Memory-Centric Architectures Enabled by RISC-V and OmniXtend

This article discusses technologies for memory-centric computing and introduces OmniXtend, a cache coherence protocol.

July 09, 2019 by Ted Marena, Western Digital

How Data-Centric Applications Can Capitalize on RISC-V Processor Innovation

This article explores how RISC-V, combined with open-source collaboration and standards, is enabling innovation and purpose-built technologies among software engineers, system architects, CTOs, and board designers. It also touches on the possible impact that RISC-V and open source trends could have on the future of data-centric application experiences.

March 20, 2019 by Ted Marena, Western Digital

How to Utilize the RISC-V Instruction Set CKB-VM

Part 3 of this series shows examples of the CKB-VM, a RISC-V instruction set based VM, in action in three different ways.

March 19, 2019 by Xuejie Xiao, Nervos

CKB-VM as a RISC-V Instruction Set: Inspiration, Design, and Benefits

Learn about CKB-virtual machine (VM), which is a RISC-V instruction set that utilizes RISC-V's open-source instruction set architecture.

March 12, 2019 by Xuejie Xiao, Nervos

Introduction to the RISC-V Instruction Set CKB-VM and its Requirements

The Nervos CKB-Virtual Machine (CKB-VM) is a RISC-V instruction set based VM for executing smart contracts on Nervos CKB, written in Rust.

March 05, 2019 by Xuejie Xiao, Nervos

Getting Started with the Verilog Hardware Description Language

In this article, we’ll study the basic structure of a Verilog module, look at some examples of using the Verilog “wire” data type and its vector form, and briefly touch on some differences between VHDL and Verilog.

January 05, 2019 by Dr. Steve Arar

Clock Signals in FPGA Design: Data Path Maximal Clock Rates and the Xilinx PERIOD Timing Constraint

This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock signal that will be used with an FPGA design.

December 05, 2018 by Dr. Steve Arar

Intro Software Walkthrough: Fast Fourier Transforms and the Xilinx FFT IP Core

This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and function as a basic walkthrough of the Fast Fourier Transform interface.

October 17, 2018 by Dr. Steve Arar

The Electrical Engineer’s Guide to Instruction Set Architectures (ISAs)

This article explores some important details related to the design and functionality of processors.

August 15, 2018 by Robert Keim

Considerations for Adding Reset Capability to an FPGA Design

This article will look at some of the consequences of adding a reset input to an FPGA design.

July 30, 2018 by Dr. Steve Arar

Use the Xilinx System Generator to Implement a Simple DDS

In this article, we’ll discuss implementing a simple direct digital synthesizer (DDS) using the Xilinx System Generator.

July 02, 2018 by Dr. Steve Arar

RISC-V: Opening a New Era of Innovation for Embedded Design

This article explores the benefits behind RISC-V's open-source hardware model, discussing it's longevity, portability, and reliability.

June 27, 2018 by Ted Marena, Microsemi

Use the Xilinx CORDIC Core to Easily Generate Sine and Cosine Functions

This article will review integrating a Xilinx IP core into an FPGA design.

May 02, 2018 by Dr. Steve Arar

Utilizing Xilinx’s MicroBlaze in FPGA Design

MicroBlaze is a 32-bit soft RISC processor core, created to accelerate the development of cost-sensitive, high-volume applications that traditionally required one or more microcontrollers.

April 27, 2018 by Xilinx

RISC-V: Transforming the Development of SoC Devices that Combine FPGAs and Microcontrollers

Until recently, developers integrating a FPGA fabric with a microcontroller were severely limited in their choice of IP licensing options. Using open-source tools with a RISC-V core in a FPGA is present a solution to that problem.

September 06, 2017 by Ted Marena, Microsemi