Latest FPGA Technical Articles

In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.

In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.

This article demonstrates the operation of an LTspice shift register and discusses details of its schematic and timing…

This article demonstrates the operation of an LTspice shift register and discusses details of its schematic and timing relationships.

Customizing the device parameters of LTspice's logic gates and flip-flops can help you more accurately simulate these…

Customizing the device parameters of LTspice's logic gates and flip-flops can help you more accurately simulate these components. This article walks through the specification process and provides some helpful tips.

This article explains how to successfully integrate logic gates into an LTspice simulation.

This article explains how to successfully integrate logic gates into an LTspice simulation.

Indispensable for modern electrical engineering, application-specific integrated circuits (ASICs) form a diverse group of…

Indispensable for modern electrical engineering, application-specific integrated circuits (ASICs) form a diverse group of integrated circuits (ICs) that help designers to optimize sophisticated electronic devices.

This brief gives an overview of the steps in a typical mixed-signal IC design flow.

This brief gives an overview of the steps in a typical mixed-signal IC design flow.

Learn the high-level overview of digital integrated circuit (IC) design.

Learn the high-level overview of digital integrated circuit (IC) design.

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.

The design of a modern IC is a truly monumental undertaking, and IC design tools make the job possible.

In this article, we’ll study the basic structure of a Verilog module, look at some examples of using the Verilog…

In this article, we’ll study the basic structure of a Verilog module, look at some examples of using the Verilog “wire” data type and its vector form, and briefly touch on some differences between VHDL and Verilog.

This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock…

This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock signal that will be used with an FPGA design.

This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and…

This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and function as a basic walkthrough of the Fast Fourier Transform interface.

This article explores some important details related to the design and functionality of processors.

This article explores some important details related to the design and functionality of processors.

This article will look at some of the consequences of adding a reset input to an FPGA design.

This article will look at some of the consequences of adding a reset input to an FPGA design.

In this article, we’ll discuss implementing a simple direct digital synthesizer (DDS) using the Xilinx System Generator.

In this article, we’ll discuss implementing a simple direct digital synthesizer (DDS) using the Xilinx System Generator.

This article will review integrating a Xilinx IP core into an FPGA design.

This article will review integrating a Xilinx IP core into an FPGA design.

In this article, we discuss metastability, setup time, and hold time in designing a digital VLSI circuit.

In this article, we discuss metastability, setup time, and hold time in designing a digital VLSI circuit.

An FPGA is a crucial tool for many DSP and embedded systems engineers. However, the learning curve when getting started…

An FPGA is a crucial tool for many DSP and embedded systems engineers. However, the learning curve when getting started can be fairly steep. This project introduces the Quartus II and ModelSim software suites as well as a background on FPGA design flow for system on chip development. The development board used was a Terasic DE1-SoC, which has the Altera Cyclone V SoC chip. This IC contains an FPGA and an integrated ARM Cortex A9 as a hard processor system.