Connect with us
×
ARTICLES
LATEST
NEWS
PROJECTS
TECHNICAL ARTICLES
NEW INDUSTRY PRODUCTS
Forum
LATEST
GENERAL ELECTRONICS
CIRCUITS & PROJECTS
EMBEDDED & MICRO
COMMUNITY
Education
Textbooks
Video Lectures
Worksheets
Industry Webinars
Industry Training
Tools
Calculators
Part Search
Test Equipment DB
BOM Tool
Datasheet Search
Giveaways
Test Db
Part Search
LOG IN / JOIN
Log In
Join AAC
Sign in with
Member Benefits
Log In
Join AAC
Sign in with
Member Benefits
Home
Technical Articles
Digital ICs
Categories
Digital ICs Technical Articles
All
News
Projects
Technical
Articles
Latest
Most Viewed
Education
Latest
Analog
Automotive
Connectors
Digital IC's
Electro mechanical
Embedded
IoT
Power
RF
Sensors
Test & Measurement
Wearables
Pipelined Direct Form FIR Versus the Transposed Structure
This article will review two pipelined structures to implement a high throughput FIR filter.
18 hours ago
by
Steve Arar
Considerations for FPGA Implementation of LinearPhase FIR Filters
This article will review considerations for efficient FPGA implementation of symmetric FIR filters.
4 days ago
by
Steve Arar
Introduction to Distributed Arithmetic
This article will review the distributed arithmetic which is an interesting method of efficiently implementing multiplyandaccumulate operations....
May 11, 2018
by
Steve Arar
Basic Binary Division: The Algorithm and the VHDL Code
This article will review a basic algorithm for binary division.
May 09, 2018
by
Steve Arar
Use the Xilinx CORDIC Core to Easily Generate Sine and Cosine Functions
This article will review integrating a Xilinx IP core into an FPGA design.
May 02, 2018
by
Steve Arar
How Does Xilinx Use Its Logic Fabric to Implement Efficient Multipliers?
This article will review the structure of the binary multipliers that use the lookup tables (LUTs) in the Xilinx logic fabric.
April 30, 2018
by
Steve Arar
T Is for Toggle: Understanding the T FlipFlop
This tech brief provides an overview of a somewhat uncommon member of the flipflop family.
April 17, 2018
by
Robert Keim
How to Use CarrySave Adders to Efficiently Implement Multioperand Addition
This article reviews the use of carrysave adders to efficiently compute a multioperand addition.
April 13, 2018
by
Steve Arar
How to Use VHDL Components to Create a Neat Hierarchical Design
This article defines VHDL components, describes component declaration, and gives examples of how to use VHDL components in your code. It also touches on the "forgenerate" statement and its...
April 06, 2018
by
Steve Arar
How to Write the VHDL Description of a Simple Algorithm: The Control Path
This article will review converting a simple algorithm into a VHDL description.
March 16, 2018
by
Steve Arar
How to Write the VHDL Description of a Simple Algorithm: The Data Path
In this article, you'll learn how to write the VHDL code for a simple algorithm.
March 15, 2018
by
Steve Arar
How to Reduce Power Consumption with Clock Gating
This article will discuss the basic concepts of clock gating and how it can be used to reduce the power consumption of synchronous digital systems....
March 08, 2018
by
Steve Arar
Encoding the States of a Finite State Machine in VHDL
This article will review different encoding methods that can be used to implement the states of an FSM.
March 05, 2018
by
Steve Arar
Incomplete If Statements and Latch Inference in VHDL
In this article, we’ll see that a memory element can be unintentionally inferred from an incomplete “if” statement.
February 23, 2018
by
Steve Arar
Sequential VHDL: If and Case Statements
This article will review two important sequential statements in VHDL, namely “if” and “case” statements.
February 21, 2018
by
Steve Arar
The Why and How of Pipelining in FPGAs
This article explains pipelining and its implications with respect to FPGAs, i.e., latency, throughput, change in operating frequency, and resource utilization....
February 15, 2018
by
Sneha H.L.
The Variable: A Valuable Object in Sequential VHDL
This article will discuss the important features of variables in VHDL.
February 14, 2018
by
Steve Arar
Introduction to Sequential VHDL Statements
This article will try to develop a better understanding of the sequential statement’s importance in VHDL.
February 09, 2018
by
Steve Arar
Review of VHDL Signed/Unsigned Data Types
This article will review the “signed”/“unsigned” data types.
February 01, 2018
by
Steve Arar
Integer and Its Subtypes in VHDL
This article will discuss the VHDL integer data type.
January 29, 2018
by
Steve Arar
Page 1 of 4
Next Page →
Continue to site
Quote of
the day
“
”
