Latest IC Design Technical Articles

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Physically Unclonable Functions: Classification, Evaluation, and Tradeoffs in PUFs

In this article, we’ll take a deeper look at how PUFs are classified, the attributes that make a “good” PUF, and design tradeoffs.

July 18, 2021 by Jake Hertz

An Introduction to Physically Unclonable Functions

In this article, we’ll discuss the PUF or physically unclonable function and how it boosts hardware security in ICs.

June 14, 2021 by Jake Hertz

An Introduction to Switched-capacitor Circuits

In this series of articles, we’ll discuss one of the fundamental building blocks of analog IC design: the switched-capacitor circuit.

April 21, 2021 by Jake Hertz

Modeling Hysteresis in SPICE

Modeling hysteresis in SPICE can be difficult when you're dealing with a multivalued transfer function. In this article, we'll teach you a way to "cheat" to get around this issue.

January 22, 2021 by Kevin Aylward

How Junction-to-Ambient Thermal Resistance of an IC Package Affects Thermal Performance

Assessing the thermal performance of an IC package becomes easier if you understand this common, but often misapplied, parameter known as theta JA.

December 27, 2020 by Dr. Steve Arar

Basics of IC Design Flows

This series will give you foundational information about the concept of integrated circuit (IC) design flows across types of IC.

December 09, 2020 by Jean-Jacques DeLisle

What Is Mixed-Signal IC Design?

This brief gives an overview of the steps in a typical mixed-signal IC design flow.

December 07, 2020 by Jean-Jacques DeLisle

What Is RF Integrated Circuit Design?

Learn the high-level steps behind RFIC design.

December 06, 2020 by Jean-Jacques DeLisle

What Is Analog IC Design?

Learn the basic steps of the analog IC design process and how it compares to digital IC design.

December 04, 2020 by Jean-Jacques DeLisle

What Is Digital IC Design?

Learn the high-level overview of digital integrated circuit (IC) design.

December 02, 2020 by Jean-Jacques DeLisle

Transistor Sizing in VLSI Design Using the Linear Delay Model

In this article, we will learn how to find the optimal size of a transistor/logic gate present in a larger circuit to provide the desired performance using the linear delay model.

November 16, 2020 by Tosin Jemilehin

The Elmore Delay Model in VLSI Design

In this article, we'll discuss the Elmore delay model, which provides a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.

November 11, 2020 by Tosin Jemilehin

Introduction to CMOS Image Sensors

In this article, you'll learn the basics of the CMOS image sensor, including its core components, its block diagram, its strengths and weaknesses, and its applications.

November 09, 2020 by Dr. Steve Arar

The Linear RC-Delay Model in VLSI Design

In this article, we'll discuss how a single transistor can be sized to properly integrate with other transistors to provide optimal performance in terms of speed and power.

November 02, 2020 by Tosin Jemilehin

The Effect of MOS Non-Idealities on VLSI Circuit Reliability

Learn about various non-idealities of MOS transistors and the effects they have on VLSI system reliability.

October 06, 2020 by Tosin Jemilehin

Non-Idealities in VLSI Circuits

This article discusses VLSI (very-large-scale integration) circuits and the sources of non-idealities that affect MOS transistors.

September 29, 2020 by Tosin Jemilehin

Designing I/O Drivers for Integrated Circuit I2C Modules

This article discusses designing input/output drivers for integrated circuit I2C modules.

August 05, 2020 by Chandana Krishna

An Example of Securing In-Cabin AI using TEE on a Secure FPGA SoC

This article discusses trusted execution environments — already used in a variety of connected devices — by showing how using TEE and an FPGA SoC can work in vehicle in-cabin AI.

July 28, 2020 by Katherine Hsu, Hex-Five Security

How Semiconductor Manufacturing Benefits from Smart Fabs

Semiconductor manufacturing is a complex industry and small improvements anywhere in the process can make a big difference to the bottom line. This article discusses the benefits of continually optimizing manufacturing for the semiconductor industry by introducing smart manufacturing solutions.

May 19, 2020 by Tim Hewitt, Siemens Digital Industries Software

The Role of Last-Level Cache Implementation for SoC Developers

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

May 12, 2020 by Kurt Shuler, Arteris