Latest EDA Tools Articles and Videos

Learn how to build a constant-bandwidth band-pass filter covering 20 kHz to 60 kHz, with an integrated frequency counter…

Learn how to build a constant-bandwidth band-pass filter covering 20 kHz to 60 kHz, with an integrated frequency counter for precise tuning.

Sending static PDFs and Gerbers for feedback is killing your project timelines and leading to costly PCB rework. Learn…

Sending static PDFs and Gerbers for feedback is killing your project timelines and leading to costly PCB rework. Learn how to break down engineering silos and modernize your PCB design reviews.

This project brief describes how to build a wide-range DC-DC buck converter capable of delivering a regulated 5.0 or 3.3…

This project brief describes how to build a wide-range DC-DC buck converter capable of delivering a regulated 5.0 or 3.3 V output from input voltages ranging from 7 to 60 V.

Sergiy Nesterenko, founder and CEO of Quilter, discusses his journey from SpaceX to creating an AI platform that uses…

Sergiy Nesterenko, founder and CEO of Quilter, discusses his journey from SpaceX to creating an AI platform that uses reinforcement learning and computational physics to fully automate complex PCB layouts.

In this article, we'll learn how to calculate the noise power and signal-to-noise ratio (SNR) of a double-sideband…

In this article, we'll learn how to calculate the noise power and signal-to-noise ratio (SNR) of a double-sideband suppressed-carrier communication system.

This project brief describes how to assemble an isolated half-bridge IGBT gate driver module built around the…

This project brief describes how to assemble an isolated half-bridge IGBT gate driver module built around the NCD57085DR2G. It features onboard current sensing and overcurrent protection.

In this Tech Guide, learn how the Vishay ISO-AC-VSAO Reference Design enables accurate, isolated high-voltage AC…

In this Tech Guide, learn how the Vishay ISO-AC-VSAO Reference Design enables accurate, isolated high-voltage AC measurement. Watch now to get started!

The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs

The new version of FPGA AI Suite is designed to accelerate trained AI models into FPGAs

Learn how SoC integration impacts SMT assembly yield, from fine-pitch BGA challenges and package warpage to reflow…

Learn how SoC integration impacts SMT assembly yield, from fine-pitch BGA challenges and package warpage to reflow profiling and inspection strategies.

HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to…

HDLs are formal descriptions of behavior, making them software by definition. Modernizing these outdated tools is key to making FPGA development more accessible and productive for all engineers.

Modern SoC Evaluation Boards demand high-performance design, SI/PI, and system validation. Faraday offers 3 flexible…

Modern SoC Evaluation Boards demand high-performance design, SI/PI, and system validation. Faraday offers 3 flexible service levels to meet these complexities.

Learn how to prevent costly assembly delays by synchronizing ECAD and MCAD workflows through continuous 3D validation.…

Learn how to prevent costly assembly delays by synchronizing ECAD and MCAD workflows through continuous 3D validation. This also stabilizes production and eliminates mid-cycle re-spins.

Advanced packaging is at a crossroads due to AI demand. Learn the four emerging paths—CoWoS, CoPoS, glass-core, and…

Advanced packaging is at a crossroads due to AI demand. Learn the four emerging paths—CoWoS, CoPoS, glass-core, and CoWoP—and how to choose the right one for your multi-die system design.

The Renesas 365 Development platform unifies electronics design from MCU recommendation to validation.

The Renesas 365 Development platform unifies electronics design from MCU recommendation to validation.

A new human-centered toolkit includes goal-driven autonomous agents within established verification environments.

A new human-centered toolkit includes goal-driven autonomous agents within established verification environments.

The shift to 3D ICs and chiplets demands automated, hierarchical design planning to manage exploding pin counts. Learn…

The shift to 3D ICs and chiplets demands automated, hierarchical design planning to manage exploding pin counts. Learn how Siemens EDA's Innovator3D IC addresses these challenges.

Announced today, the free cloud-based toolset replaces spreadsheets with graphical signal path design for automated test…

Announced today, the free cloud-based toolset replaces spreadsheets with graphical signal path design for automated test engineers.

The W3510E workflow targets pre-layout modeling, EM analysis, and early UCIe and BoW validation for advanced AI…

The W3510E workflow targets pre-layout modeling, EM analysis, and early UCIe and BoW validation for advanced AI infrastructure designs.

The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article…

The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this time-consuming process using automation.