The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this…
The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this time-consuming process using automation.
Learn how scaling beyond Dennard's limits triggered short-channel effects (SCE) and why transitioning from FinFET to…
Learn how scaling beyond Dennard's limits triggered short-channel effects (SCE) and why transitioning from FinFET to Gate-All-Around (GAA) architectures is vital for 2 nm control.
This article explores the Gilbert cell, a widely used analog multiplier circuit.
This article explores the Gilbert cell, a widely used analog multiplier circuit.
Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification,…
Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification, delivering a 10X productivity increase.
Learn how to select the zero frequency, damping factor, and loop bandwidth for one of the most popular PLL configurations.
Learn how to select the zero frequency, damping factor, and loop bandwidth for one of the most popular PLL configurations.
Singulation (wafer dicing) is critical for IC wafer manufacturing. Laser/plasma dicing is replacing mechanical methods.…
Singulation (wafer dicing) is critical for IC wafer manufacturing. Laser/plasma dicing is replacing mechanical methods. Lidrotec's laser-liquid technology offers virtually zero-damage cuts.
In this article, we examine how adding a zero to the PLL loop filter affects the transient behavior and steady-state errors.
In this article, we examine how adding a zero to the PLL loop filter affects the transient behavior and steady-state errors.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.
Learn how using a pole-zero loop filter improves PLL performance and design flexibility over the simpler lag filter.
Learn how using a pole-zero loop filter improves PLL performance and design flexibility over the simpler lag filter.
Do you remember when supercomputers were described by their processing power? That was so 2024. Today, we talk about the…
Do you remember when supercomputers were described by their processing power? That was so 2024. Today, we talk about the power for processing. Goodbye terraops, hello terrawatt-hours!
Enjoy this roundup of our favorite All About Circuits research news articles of 2025!
Enjoy this roundup of our favorite All About Circuits research news articles of 2025!
Explore our editors' top picks from 2025, featuring breakthrough AI hardware, legendary chip history, behind-the-scenes…
Explore our editors' top picks from 2025, featuring breakthrough AI hardware, legendary chip history, behind-the-scenes insights, and exclusive industry interviews.
In this article, we analyze the steady-state errors and Bode plots for a second-order PLL with a simple, first-order loop filter.
In this article, we analyze the steady-state errors and Bode plots for a second-order PLL with a simple, first-order loop filter.
FPGAs are limited by outdated proprietary software. Learn how embracing open-source tools is necessary to modernize FPGA…
FPGAs are limited by outdated proprietary software. Learn how embracing open-source tools is necessary to modernize FPGA development and unlock their full potential.
In this article, we'll use a nonlinear mathematical model to improve our understanding of how a first-order PLL locks to a signal.
In this article, we'll use a nonlinear mathematical model to improve our understanding of how a first-order PLL locks to a signal.
The phase-locked loop (PLL) is widely used in contemporary analog and digital communication systems. In this article, we…
The phase-locked loop (PLL) is widely used in contemporary analog and digital communication systems. In this article, we develop a nonlinear model for the analog PLL by analyzing its key components.
Learn how advanced RF MEMS switches with high linearity, low loss, and fast switching speeds are enabling modern cellular…
Learn how advanced RF MEMS switches with high linearity, low loss, and fast switching speeds are enabling modern cellular communication systems.
PLL demodulators are popular, easy to implement, and offer superior noise performance compared to many other FM…
PLL demodulators are popular, easy to implement, and offer superior noise performance compared to many other FM demodulator circuits. Learn how they operate in this article.
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting…
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors.
Today, the FPGA company revealed an array of new announcements at its annual Altera Innovators Day developer conference.
Today, the FPGA company revealed an array of new announcements at its annual Altera Innovators Day developer conference.
Facebook
Google
GitHub
Linkedin