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Understanding the Exclusive-OR Phase Detector

Understanding the Exclusive-OR Phase Detector

This article explores the operation of the simplest digital phase detector: the exclusive-OR (XOR) gate.


Build Your Own Clock With Analog Dials, Part 3

Build Your Own Clock With Analog Dials, Part 3

To complete this project, we add backlight control and temperature-sensing functionality to the clock we built in the previous installments.


Diode-Based Phase Detectors: Key Principles and Example Circuits

Diode-Based Phase Detectors: Key Principles and Example Circuits

We examine phase detectors that leverage either the nonlinear characteristics or switching capabilities of diodes to perform multiplication.


Breaking Down 50 Million Pins: A Smarter Way to Design 3D IC Packages

Breaking Down 50 Million Pins: A Smarter Way to Design 3D IC Packages

The shift to 3D ICs and chiplets demands automated, hierarchical design planning to manage exploding pin counts. Learn how Siemens EDA's Innovator3D IC addresses these challenges.


Build Your Own Clock With Analog Dials, Part 2

Build Your Own Clock With Analog Dials, Part 2

We continue our design of a clock that uses analog ammeters to display time and temperature. In this installment, we examine the second of the two circuits that enable the timekeeping function.


Using Gilbert Multipliers as Phase Detectors in PLLs

Using Gilbert Multipliers as Phase Detectors in PLLs

This article explores the operation of the Gilbert-cell phase detector for both small and large signals.


ElastixAI Emerges From Stealth With FPGA Approach to Gen AI Supercomputing

ElastixAI Emerges From Stealth With FPGA Approach to Gen AI Supercomputing

In this exclusive interview, the Seattle startup says its software-ML-hardware co-design—announced today—converts off-the-shelf FPGA servers into high-efficiency AI inference engines.


News Feb 25, 2026 by Luke James
Three Ways to Accelerate Cell Layout in DTCO

Three Ways to Accelerate Cell Layout in DTCO

The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this time-consuming process using automation.


Nanoscale SCE: Electrostatic Challenges and FinFET/GAA Mitigation Solutions

Nanoscale SCE: Electrostatic Challenges and FinFET/GAA Mitigation Solutions

Learn how scaling beyond Dennard's limits triggered short-channel effects (SCE) and why transitioning from FinFET to Gate-All-Around (GAA) architectures is vital for 2 nm control.


Introduction to the Gilbert Multiplier

Introduction to the Gilbert Multiplier

This article explores the Gilbert cell, a widely used analog multiplier circuit.


Cadence Unwraps Agentic AI Super Agent for Chip Design and Verification

Cadence Unwraps Agentic AI Super Agent for Chip Design and Verification

Announced today, the new ChipStack AI Super Agent from Cadence automates front end silicon design and verification, delivering a 10X productivity increase.


News Feb 10, 2026 by Duane Benson
Second-Order Type-2 PLLs: Bode Diagrams, Bandwidth, and Overshoot

Second-Order Type-2 PLLs: Bode Diagrams, Bandwidth, and Overshoot

Learn how to select the zero frequency, damping factor, and loop bandwidth for one of the most popular PLL configurations.


Singulation—Literally Cutting Edge—Is Gaining More Importance for Wafer Fabs

Singulation—Literally Cutting Edge—Is Gaining More Importance for Wafer Fabs

Singulation (wafer dicing) is critical for IC wafer manufacturing. Laser/plasma dicing is replacing mechanical methods. Lidrotec's laser-liquid technology offers virtually zero-damage cuts.


News Feb 06, 2026 by Gordon Feller
Understanding the Time-Domain Response of PLLs With Lag-Lead Filters

Understanding the Time-Domain Response of PLLs With Lag-Lead Filters

In this article, we examine how adding a zero to the PLL loop filter affects the transient behavior and steady-state errors.


Understanding the PDK Generation Process

Understanding the PDK Generation Process

In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.


Introducing the Lag-Lead Filter

Introducing the Lag-Lead Filter

Learn how using a pole-zero loop filter improves PLL performance and design flexibility over the simpler lag filter.


Our 2025 Top Trend: AI Assimilates

Our 2025 Top Trend: AI Assimilates

Do you remember when supercomputers were described by their processing power? That was so 2024. Today, we talk about the power for processing. Goodbye terraops, hello terrawatt-hours!


News Dec 28, 2025 by Dale Wilson
Our Top 2025 Research Stories: Rubber CMOS, Washable Electronics, and More

Our Top 2025 Research Stories: Rubber CMOS, Washable Electronics, and More

Enjoy this roundup of our favorite All About Circuits research news articles of 2025!


News Dec 26, 2025 by Jeff Child
From 124-Layer PCBs to the 555 Timer: Our Favorite Content of the Year

From 124-Layer PCBs to the 555 Timer: Our Favorite Content of the Year

Explore our editors' top picks from 2025, featuring breakthrough AI hardware, legendary chip history, behind-the-scenes insights, and exclusive industry interviews.


News Dec 25, 2025 by Dale Wilson
Understanding the Limitations of the Second-Order Type-1 PLL With a Lag Filter

Understanding the Limitations of the Second-Order Type-1 PLL With a Lag Filter

In this article, we analyze the steady-state errors and Bode plots for a second-order PLL with a simple, first-order loop filter.