Three hot technologies are leading the way in continuing the Moore’s Law performance increases that can no longer be achieved by transistor scaling alone.
Three hot technologies are leading the way in continuing the Moore’s Law performance increases that can no longer be achieved by transistor scaling alone.
We publish hundreds of articles every year—too many even for our team to read them all. So, we decided to share our…
We publish hundreds of articles every year—too many even for our team to read them all. So, we decided to share our favorite 2024 news, technical articles, projects, and podcasts with each other and all of you. Enjoy!
The new configuration increases computing core area within the same overall processor package dimensions.
The new configuration increases computing core area within the same overall processor package dimensions.
The quantum hardware company claims its cryo-CMOS transistor solves two critical roadblocks to quantum computing: scaling…
The quantum hardware company claims its cryo-CMOS transistor solves two critical roadblocks to quantum computing: scaling and cooling costs.
Marvell leveraged advanced process nodes for its new DSP to address the traditional shortcomings of PAM4.
Marvell leveraged advanced process nodes for its new DSP to address the traditional shortcomings of PAM4.
A new memory technology has been sweeping the industry and bringing substantial performance gains with it.
A new memory technology has been sweeping the industry and bringing substantial performance gains with it.
Announced at Electronica 2024 this week, the new source measurement unit measures nano-scale semiconductor device signals…
Announced at Electronica 2024 this week, the new source measurement unit measures nano-scale semiconductor device signals that would otherwise be drowned out by electrical noise.
The new release upgrades Xpedition, Hyperlynx, and PADS Professional with an integrated design flow and collaborative…
The new release upgrades Xpedition, Hyperlynx, and PADS Professional with an integrated design flow and collaborative user experience.
Unveiled today at Electronica, AMD designed the new FPGA to act as a “traffic cop” in larger AI systems.
Unveiled today at Electronica, AMD designed the new FPGA to act as a “traffic cop” in larger AI systems.
In this roundup, we discuss several announcements from last week's summit pushing RISC-V adoption and processing power.
In this roundup, we discuss several announcements from last week's summit pushing RISC-V adoption and processing power.
Microchip tapped SiFive's RISC-V CPUs for its new mission-critical processors.
Microchip tapped SiFive's RISC-V CPUs for its new mission-critical processors.
The new software updates make software verification more accurate and intuitive.
The new software updates make software verification more accurate and intuitive.
The startup is taking a unique approach to existing cloud and IoT challenges.
The startup is taking a unique approach to existing cloud and IoT challenges.
The Agilex 3 line includes small form-factor FPGAs with AI and an integrated MCU.
The Agilex 3 line includes small form-factor FPGAs with AI and an integrated MCU.
New memory technologies, including HBM4, DDR5 DRAM, and MRAM, each respond to various industries outgrowing current…
New memory technologies, including HBM4, DDR5 DRAM, and MRAM, each respond to various industries outgrowing current storage infrastructure.
Intel has revealed the details of the long-awaited Lunar Lake architecture, bringing advanced AI compute to personal computing.
Intel has revealed the details of the long-awaited Lunar Lake architecture, bringing advanced AI compute to personal computing.
Announced this week at Hot Chips 2024, the new processors use a scalable I/O sub-system to slash energy consumption and…
Announced this week at Hot Chips 2024, the new processors use a scalable I/O sub-system to slash energy consumption and data center footprint.
The two have joined forces to craft a fourth generation, terabit-scale Cloud/Data Center Interconnect (DCI) and metro…
The two have joined forces to craft a fourth generation, terabit-scale Cloud/Data Center Interconnect (DCI) and metro transport network solution based on Microchip’s PHY and Acacia’s module.
Startups are using and supporting AI in a myriad of ways.
Startups are using and supporting AI in a myriad of ways.
Announced today, the new RISC-V processor is SiFive's first foray into mainstream data center and infrastructure use cases.
Announced today, the new RISC-V processor is SiFive's first foray into mainstream data center and infrastructure use cases.
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