In this article, we’ll study the basic structure of a Verilog module, look at some examples of using the Verilog “wire” data type and its vector form, and briefly touch on some differences between VHDL and Verilog.
January 05, 2019 by Dr. Steve Arar
This article will discuss the Xilinx Period timing constraint that allows us to describe the characteristics of the clock signal that will be used with an FPGA design.
December 05, 2018 by Dr. Steve Arar
This article will explain some of the most important settings and design parameters for the Xilinx FFT IP core and function as a basic walkthrough of the Fast Fourier Transform interface.
October 17, 2018 by Dr. Steve Arar