Latest Technical Articles

We examine phase detectors that leverage either the nonlinear characteristics or switching capabilities of diodes to…

We examine phase detectors that leverage either the nonlinear characteristics or switching capabilities of diodes to perform multiplication.

We continue our design of a clock that uses analog ammeters to display time and temperature. In this installment, we…

We continue our design of a clock that uses analog ammeters to display time and temperature. In this installment, we examine the second of the two circuits that enable the timekeeping function.

This article explores the operation of the Gilbert-cell phase detector for both small and large signals.

This article explores the operation of the Gilbert-cell phase detector for both small and large signals.

This project turns old-school analog ammeters into a working clock that can also display the ambient temperature.

This project turns old-school analog ammeters into a working clock that can also display the ambient temperature.

The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article…

The device technology co-optimization (DTCO) methodology requires generating large numbers of layouts. This article introduces a few ways of speeding up this time-consuming process using automation.

This article explores the Gilbert cell, a widely used analog multiplier circuit.

This article explores the Gilbert cell, a widely used analog multiplier circuit.

Learn how to select the zero frequency, damping factor, and loop bandwidth for one of the most popular PLL configurations.

Learn how to select the zero frequency, damping factor, and loop bandwidth for one of the most popular PLL configurations.

This article explains how Type-2 PLLs with an integrator loop filter outperform Type-1 systems. To do so, we'll examine…

This article explains how Type-2 PLLs with an integrator loop filter outperform Type-1 systems. To do so, we'll examine the PLL behavior for frequency step and frequency ramp inputs.

In this article, we examine how adding a zero to the PLL loop filter affects the transient behavior and steady-state errors.

In this article, we examine how adding a zero to the PLL loop filter affects the transient behavior and steady-state errors.

In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.

In this article, we'll walk through the steps of generating a Process Design Kit (PDK) for digital standard cell libraries.

In this article, we derive design equations for a second-order PLL with a lag-lead filter by examining its Bode plots.

In this article, we derive design equations for a second-order PLL with a lag-lead filter by examining its Bode plots.

Learn how using a pole-zero loop filter improves PLL performance and design flexibility over the simpler lag filter.

Learn how using a pole-zero loop filter improves PLL performance and design flexibility over the simpler lag filter.

In this article, we evaluate the designs of two simple frequency synthesizers to learn how a second-order PLL with a lag…

In this article, we evaluate the designs of two simple frequency synthesizers to learn how a second-order PLL with a lag filter can provide a faster rise time than a first-order PLL.

In this article, we analyze the steady-state errors and Bode plots for a second-order PLL with a simple, first-order loop filter.

In this article, we analyze the steady-state errors and Bode plots for a second-order PLL with a simple, first-order loop filter.

Learn how adding a lowpass loop filter to a PLL with a single integrator impacts both the frequency-domain and…

Learn how adding a lowpass loop filter to a PLL with a single integrator impacts both the frequency-domain and time-domain response.

Higher-order PLLs are more commonly used than first-order PLLs. To explain why, we explore the first-order PLL's behavior…

Higher-order PLLs are more commonly used than first-order PLLs. To explain why, we explore the first-order PLL's behavior in response to two inputs: a frequency step and frequency ramp.

In this article, we'll use the linearized model of a first-order PLL to understand its response to a simple input change.…

In this article, we'll use the linearized model of a first-order PLL to understand its response to a simple input change. We'll then use Matlab simulations to visualize the signals.

In this project, we'll build and demonstrate a discrete analog solution to the incompatible logic levels of an Arduino…

In this project, we'll build and demonstrate a discrete analog solution to the incompatible logic levels of an Arduino Uno and an Elecrow e-paper HMI display.

In this article, we'll use a nonlinear mathematical model to improve our understanding of how a first-order PLL locks to a signal.

In this article, we'll use a nonlinear mathematical model to improve our understanding of how a first-order PLL locks to a signal.